公开(公告)号：US06995459B2

公开(公告)日：2006-02-07

申请号：US11063299

申请日：2005-02-22

申请人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

发明人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68377 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads. At least portions of the die paddle, the first and second leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the first leads being exposed in a common exterior surface of the package body.

摘要翻译： 根据本发明，提供了一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯片，并且包括形成在其中的至少两个槽，并沿其一对周边边缘段中的相应的一个延伸。 半导体封装还包括多个第一引线，它们分离成设置在包括在管芯焊盘中的各个槽中的至少两个组。 除了第一引线之外，半导体封装还包括多个第二引线，它们也分隔成至少两组，其间隔开的关系相对于管芯焊盘的至少两个周边边缘段的相应延伸。 电连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到第一和第二引线中的每一个的至少一些。 裸片，第一和第二引线和半导体管芯的至少一部分被封装主体封装，裸片焊盘的底表面和第一引线暴露在封装体的公共外表面中。

公开(公告)号：US06876068B1

公开(公告)日：2005-04-05

申请号：US10447012

申请日：2003-05-28

申请人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

发明人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

IPC分类号： H01L23/31 ,  H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68377 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads. At least portions of the die paddle, the first and second leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the first leads being exposed in a common exterior surface of the package body.

摘要翻译： 根据本发明，提供了一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯片，并且包括形成在其中的至少两个槽，并沿其一对周边边缘段中的相应的一个延伸。 半导体封装还包括多个第一引线，它们分离成设置在包括在管芯焊盘中的各个槽中的至少两个组。 除了第一引线之外，半导体封装还包括多个第二引线，它们也分隔成至少两组，其间隔开的关系相对于管芯焊盘的至少两个周边边缘段的相应延伸。 电连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到第一和第二引线中的每一个的至少一些。 裸片，第一和第二引线和半导体管芯的至少一部分被封装主体封装，裸片焊盘的底表面和第一引线暴露在封装体的公共外表面中。