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公开(公告)号:US20240274568A1
公开(公告)日:2024-08-15
申请号:US18496612
申请日:2023-10-27
发明人: Edgardo LABER , James Edwin VINSON
CPC分类号: H01L24/48 , H01L23/62 , H01L24/45 , H02J7/0029 , H01L23/498 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247
摘要: A package for use with an integrated circuit having a contact pad is provided. The package includes an enclosure portion; a package pin for external connection; and a protective element coupled between the contact pad and the package pin. The protective element is operable in a first state or a second state. In the first state the protective element passes a current between the contact pad and the package pin. When the current is above a threshold value the protective element changes from the first state to the second state to prevent the current from flowing between the contact pad and the package pin.
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公开(公告)号:US12062618B2
公开(公告)日:2024-08-13
申请号:US18524118
申请日:2023-11-30
申请人: Ping-Jung Yang
发明人: Ping-Jung Yang
IPC分类号: H01L23/538 , H01L23/15 , H01L23/498 , H10K77/10 , H01L23/00 , H01L25/16
CPC分类号: H01L23/5384 , H01L23/15 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H10K77/10 , C09K2323/00 , C09K2323/03 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/16 , H01L2224/03462 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05572 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11334 , H01L2224/1146 , H01L2224/11462 , H01L2224/13005 , H01L2224/13022 , H01L2224/13076 , H01L2224/1308 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16147 , H01L2224/16237 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48228 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2924/12042 , H01L2924/12044 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , Y02E10/549 , H01L2224/48091 , H01L2924/00014 , H01L2924/30107 , H01L2924/00 , H01L2224/13147 , H01L2924/00014 , H01L2224/13155 , H01L2924/00014 , H01L2224/1308 , H01L2924/00014 , H01L2224/05124 , H01L2924/00014 , H01L2224/05147 , H01L2924/00014 , H01L2224/2919 , H01L2924/00014 , H01L2224/131 , H01L2924/014 , H01L2924/1461 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2924/15311 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2224/48465 , H01L2224/48091 , H01L2924/00012 , H01L2224/48465 , H01L2224/48227 , H01L2924/00012 , H01L2224/05647 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/05655 , H01L2924/00014 , H01L2224/13144 , H01L2924/0105 , H01L2924/014 , H01L2224/13111 , H01L2924/01047 , H01L2924/014 , H01L2224/13109 , H01L2924/014 , H01L2224/13111 , H01L2924/01083 , H01L2924/014 , H01L2224/13005 , H01L2924/206 , H01L2224/13005 , H01L2924/207 , H01L2224/03462 , H01L2924/00014 , H01L2224/1146 , H01L2924/00014 , H01L2224/11334 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/05624 , H01L2924/00014 , H01L2224/45144 , H01L2924/01029 , H01L2224/45139 , H01L2924/00014 , H01L2924/12044 , H01L2924/00 , H01L2924/181 , H01L2924/00012 , H01L2224/13111 , H01L2924/01047 , H01L2924/01029 , H01L2924/014 , H01L2224/48465 , H01L2224/48227 , H01L2924/00 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00 , H01L2224/48465 , H01L2224/48091 , H01L2924/00 , H01L2924/15311 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00 , H01L2224/13144 , H01L2924/00014 , H01L2224/13111 , H01L2924/00014 , H01L2224/45147 , H01L2924/00014 , H01L2224/45144 , H01L2924/00014 , H01L2224/45124 , H01L2924/00014
摘要: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.
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公开(公告)号:US20240244750A1
公开(公告)日:2024-07-18
申请号:US18429848
申请日:2024-02-01
申请人: ROHM CO., LTD.
发明人: Masashi HAYASHIGUCHI
CPC分类号: H05K1/144 , H01L23/49811 , H01L25/115 , H05K1/18 , H01L23/40 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L2224/37011 , H01L2224/37147 , H01L2224/40137 , H01L2224/40225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48225 , H01R12/718 , H05K2201/10166 , H05K2201/10871
摘要: A semiconductor module includes: a plurality of semiconductor devices that each include a signal terminal extending in a first direction, and that is electrically connected to a semiconductor element; a heat sink; a plurality of first wiring boards that are electrically connected to the plurality of signal terminals of the respective semiconductor devices; and a second wiring board electrically connected to the plurality of first wiring boards. The signal terminal of one of the plurality of semiconductor devices is press-fitted into one of the plurality of first wiring boards in the first direction. The semiconductor module further includes a plurality of communication wirings electrically connecting the plurality of first wiring boards and the second wiring board. The plurality of communication wirings are displaceable in a direction perpendicular to the first direction.
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公开(公告)号:US20240243082A1
公开(公告)日:2024-07-18
申请号:US18400164
申请日:2023-12-29
申请人: NEC Corporation
发明人: Tomohiro YAMAJI , Ayuka TADA
CPC分类号: H01L24/05 , H01L24/04 , H01L24/45 , H01L24/48 , H01L24/49 , H10N60/80 , H01L2224/04042 , H01L2224/05552 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/49111 , H01L2224/49176
摘要: Provided is a quantum chip that includes a substrate, a superconducting layer formed on a surface of the substrate, an electrode formed on a surface of the superconducting layer along an outer edge of the substrate, and a periodic structure formed on a surface of the superconducting layer along an outer edge of the substrate.
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公开(公告)号:US12027465B2
公开(公告)日:2024-07-02
申请号:US17952838
申请日:2022-09-26
发明人: Christopher Wyland
IPC分类号: H01L23/538 , H01L23/00 , H01L23/522 , H01L23/66 , H01P1/04 , H05K1/02
CPC分类号: H01L23/5383 , H01L23/5226 , H01L23/5387 , H01L23/66 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/86 , H01L24/91 , H01P1/047 , H05K1/0243 , H01L24/45 , H01L2223/6611 , H01L2223/6627 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4805 , H01L2224/48091 , H01L2224/48135 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/49052 , H01L2224/49111 , H01L2224/49174 , H01L2224/49175 , H01L2224/73265 , H01L2224/85207 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/1903 , H01L2924/19032 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K2203/049 , H01L2224/45124 , H01L2924/00014 , H01L2224/45144 , H01L2924/00014 , H01L2224/45147 , H01L2924/00014 , H01L2224/48091 , H01L2924/00014 , H01L2224/45015 , H01L2924/20755 , H01L2224/45015 , H01L2924/20754 , H01L2224/45015 , H01L2924/20753 , H01L2224/45015 , H01L2924/20752 , H01L2224/45015 , H01L2924/20751 , H01L2224/49111 , H01L2224/48472 , H01L2924/00 , H01L2224/48472 , H01L2224/48091 , H01L2924/00 , H01L2924/01015 , H01L2924/00 , H01L2924/30111 , H01L2924/00 , H01L2224/85207 , H01L2924/00 , H01L2224/49175 , H01L2224/48472 , H01L2924/00 , H01L2924/00014 , H01L2224/85399 , H01L2924/00014 , H01L2224/05599 , H01L2224/45014 , H01L2924/206
摘要: A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.
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公开(公告)号:US20240178125A1
公开(公告)日:2024-05-30
申请号:US18071164
申请日:2022-11-29
发明人: Masamitsu Matsuura
IPC分类号: H01L23/498 , H01L21/48 , H01L23/00 , H01L23/31
CPC分类号: H01L23/49861 , H01L21/4803 , H01L23/3121 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L21/561 , H01L2224/04042 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/29006 , H01L2224/29012 , H01L2224/29014 , H01L2224/2919 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48106 , H01L2224/48225 , H01L2224/48464 , H01L2224/48465 , H01L2224/48479 , H01L2224/4848 , H01L2224/49175 , H01L2224/73265 , H01L2224/83192 , H01L2224/83395 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/85181 , H01L2224/85186 , H01L2224/85205 , H01L2224/85395 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/8546 , H01L2224/85464 , H01L2224/92247 , H01L2224/97 , H01L2924/01404 , H01L2924/0665
摘要: In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.
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7.
公开(公告)号:US20240178040A1
公开(公告)日:2024-05-30
申请号:US18389577
申请日:2023-11-14
申请人: Monolithic 3D Inc.
发明人: Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC分类号: H01L21/683 , G11C8/16 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/00 , H01L23/367 , H01L23/48 , H01L23/525 , H01L25/00 , H01L25/065 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , H10B10/00 , H10B12/00 , H10B20/00 , H10B20/20 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40
CPC分类号: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H10B10/00 , H10B10/125 , H10B12/053 , H10B12/09 , H10B12/20 , H10B12/50 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/3677 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/1214 , H01L27/1266 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H10B12/05 , H10B20/20
摘要: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.
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公开(公告)号:US20240170319A1
公开(公告)日:2024-05-23
申请号:US18542757
申请日:2023-12-17
申请人: Monolithic 3D Inc.
发明人: Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC分类号: H01L21/683 , G11C8/16 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/00 , H01L23/367 , H01L23/48 , H01L23/525 , H01L25/00 , H01L25/065 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , H10B10/00 , H10B12/00 , H10B20/00 , H10B20/20 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40
CPC分类号: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H10B10/00 , H10B10/125 , H10B12/053 , H10B12/09 , H10B12/20 , H10B12/50 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/3677 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/1214 , H01L27/1266 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H10B12/05 , H10B20/20
摘要: 3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.
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9.
公开(公告)号:US20240136309A1
公开(公告)日:2024-04-25
申请号:US18359096
申请日:2023-07-25
CPC分类号: H01L24/05 , H01L23/49 , H01L24/03 , H01L24/04 , H01L24/45 , H01L24/48 , H02M7/44 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/03334 , H01L2224/037 , H01L2224/0381 , H01L2224/04042 , H01L2224/05083 , H01L2224/05124 , H01L2224/05138 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05553 , H01L2224/05573 , H01L2224/05582 , H01L2224/05584 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0566 , H01L2224/29124 , H01L2224/29147 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01014 , H01L2924/0132 , H01L2924/01402 , H01L2924/04941 , H01L2924/04953 , H01L2924/10272 , H01L2924/1033 , H01L2924/12036 , H01L2924/13055 , H01L2924/13091
摘要: Provided is a semiconductor device with higher reliability and longer life which can suppress an increase in production costs. A semiconductor device includes: a semiconductor element; a top electrode on an upper surface of the semiconductor element; and a conductive metal plate containing copper as a main component and solid-state diffusion bonded to the top electrode of the semiconductor element.
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公开(公告)号:US20240128215A1
公开(公告)日:2024-04-18
申请号:US18485565
申请日:2023-10-12
发明人: Takashi NOMA , Shinzo ISHIBE
IPC分类号: H01L23/00
CPC分类号: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/85 , H01L24/13 , H01L24/73 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05155 , H01L2224/05164 , H01L2224/05583 , H01L2224/05644 , H01L2224/11 , H01L2224/131 , H01L2224/45124 , H01L2224/73207 , H01L2224/8584
摘要: A device may include an insulating layer disposed on a frontside of a semiconductor layer, and may include a first conductive contact disposed in a first opening in the insulating layer. The device may include a second conductive contact disposed in a second opening in the insulating layer, and may include a stacked conductive layer disposed on the first conductive contact and excluded from the second conductive contact.
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