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    Method for fabricating silicon-on-insulator device wafer
    1.
    发明授权
    Method for fabricating silicon-on-insulator device wafer 失效
    绝缘体上硅器件制造方法

    公开(公告)号：US5810994A

    公开(公告)日：1998-09-22

    申请号：US725620

    申请日：1996-10-03

    申请人： Ho Jun Lee ,  Choong Ki Kim ,  Chul Hi Han

    发明人： Ho Jun Lee ,  Choong Ki Kim ,  Chul Hi Han

    IPC分类号： B32B7/02 ,  C25F3/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/762 ,  H01L27/12

    CPC分类号： C25F3/12 ,  H01L21/2007 ,  H01L21/76251

    摘要： A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.

    摘要翻译： 绝缘体上硅器件晶片，具有均匀厚度的非常薄的单晶膜。 其通过通孔技术制造，其中在蚀刻装置中用基底硅蚀刻溶液蚀刻绝缘体上的单晶硅膜，通过以这样的方式施加通孔，使得该溶液可以用作阳极，并且SOI结构的衬底作为 一个阴极。 绝缘体的存在在单晶硅膜的下部区域和衬底中的电子产生空位，使得充满空位的下部区域不被基底硅蚀刻溶液除去，从而留下高度均匀的薄单晶硅 电影。

    Method for the prevention of misfit dislocation in silicon wafer and silicon wafer structure manufactured thereby
    2.
    发明授权
    Method for the prevention of misfit dislocation in silicon wafer and silicon wafer structure manufactured thereby 失效
    用于防止由此制造的硅晶片和硅晶片结构中的错配错位的方法

    公开(公告)号：US5828114A

    公开(公告)日：1998-10-27

    申请号：US807825

    申请日：1997-02-27

    申请人： Choong Ki Kim ,  Chul Hi Han ,  Ho Jun Lee

    发明人： Choong Ki Kim ,  Chul Hi Han ,  Ho Jun Lee

    IPC分类号： H01L21/22 ,  B81B1/00 ,  B81C99/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L21/26513 ,  H01L21/266 ,  Y10S438/938

    摘要： There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity. Formation of an impurity-blocked region in the wafer barricades the propagation of misfit dislocation because the propagation energy is not supplied in this region. Thus, the area of the silicon wafer enclosed by the impurity-blocked region has no misfit dislocation. By such conception, a silicon wafer free of misfit dislocation can be manufactured. Therefore, there are improved in electrical and mechanical properties in electrical devices, X-ray masks and micromachines as well as in surface roughness.

    摘要翻译： 公开了防止硅晶片中的错配位错的方法以及由此制造的硅晶片结构。 根据实施例的方法包括以下步骤：在化学气相沉积工艺中在硅晶片上沉积覆盖氧化硅或氮化硅; 选择性地蚀刻氧化硅或氮化硅，以形成接近形状的氧化硅或氮化硅图案; 并且以CVD硅氧化物或氮化硅图案为掩模以高密度注入硅晶片以形成杂质阻挡区域，通过掩模的作用形成在CVD二氧化硅或氮化硅的下面 。 错配位错主要从晶片的边缘传播，杂质阻挡区域可以防止传播。 传播能量实际上基于归因于杂质注入的拉伸应力。 由于在该区域不提供传播能量，所以晶片中杂质阻挡区域的形成阻碍了错配位错的传播。 因此，由杂质阻挡区域包围的硅晶片的面积没有失配位错。 通过这样的概念，可以制造没有失配位错的硅晶片。 因此，电气设备，X射线掩模和微机械以及表面粗糙度的电气和机械性能都有所提高。

    Method for the prevention of misfit dislocation in silicon wafer and silicon structure manufactured thereby
    5.
    发明授权
    Method for the prevention of misfit dislocation in silicon wafer and silicon structure manufactured thereby 失效
    防止硅晶片失配错位的方法和由此制造的硅结构

    公开(公告)号：US5801085A

    公开(公告)日：1998-09-01

    申请号：US535454

    申请日：1995-09-28

    申请人： Choong Ki Kim ,  Chul Hi Han ,  Ho Jun Lee

    发明人： Choong Ki Kim ,  Chul Hi Han ,  Ho Jun Lee

    IPC分类号： H01L21/22 ,  B81B1/00 ,  B81C99/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/266 ,  Y10S438/938

    摘要： There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity. Formation of an impurity-blocked region in the wafer barricades the propagation of misfit dislocation because the propagation energy is not supplied in this region. Thus, the area of the silicon wafer enclosed by the impurity-blocked region has no misfit dislocation. By such conception, a silicon wafer free of misfit dislocation can be manufactured. Therefore, there are improved in electrical and mechanical properties in electrical devices, X-ray masks and micromachines as well as in surface roughness.

    摘要翻译： 公开了防止硅晶片中的错配位错的方法以及由此制造的硅晶片结构。 根据实施例的方法包括以下步骤：在化学气相沉积工艺中在硅晶片上沉积覆盖氧化硅或氮化硅; 选择性地蚀刻氧化硅或氮化硅，以形成接近形状的氧化硅或氮化硅图案; 并且以CVD硅氧化物或氮化硅图案为掩模以高密度注入硅晶片以形成杂质阻挡区域，通过掩模的作用形成在CVD二氧化硅或氮化硅的下面 。 错配位错主要从晶片的边缘传播，杂质阻挡区域可以防止传播。 传播能量实际上基于归因于杂质注入的拉伸应力。 由于在该区域不提供传播能量，所以晶片中杂质阻挡区域的形成阻碍了错配位错的传播。 因此，由杂质阻挡区域包围的硅晶片的面积没有失配位错。 通过这样的概念，可以制造没有失配位错的硅晶片。 因此，电气设备，X射线掩模和微机械以及表面粗糙度的电气和机械性能都有所提高。

    Method for manufacturing a semiconductor device having a metal layer floating over a substrate
    6.
    发明授权
    Method for manufacturing a semiconductor device having a metal layer floating over a substrate 失效
    一种制造半导体器件的方法，该半导体器件具有在衬底上漂浮的金属层

    公开(公告)号：US06518165B1

    公开(公告)日：2003-02-11

    申请号：US09763401

    申请日：2001-02-22

    申请人： Jun Bo Yoon ,  Chul Hi Han ,  Eui Sik Yoon ,  Choong Ki Kim

    发明人： Jun Bo Yoon ,  Chul Hi Han ,  Eui Sik Yoon ,  Choong Ki Kim

    IPC分类号： H01L214763

    CPC分类号： H01L23/645 ,  H01L23/522 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According to the present invention, a first metal layer is formed on the substrate, a first masking layer is formed on a portion of the first metal layer, a second metal layer is formed on other portion of the first metal layer on which the first masking layer is not formed, and a second masking layer is formed on the first masking layer and the second metal layer. Then, the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer is removed, a third metal layer is formed on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer. Finally, the second masking layer, the second metal layer; and the first metal layer except a portion which the third metal layer covers are removed. In this way, the area for integrating various passive elements can be saved and the overall area for the semiconductor device including the integrated circuit and the passive elements may be reduced.

    摘要翻译： 一种用于制造半导体器件的方法，其中诸如电感器的无源元件在其上形成集成电路的衬底上浮动，使得半导体器件的总体面积可以大大降低。 根据本发明，在基板上形成第一金属层，在第一金属层的一部分上形成第一掩模层，在第一金属层的第一掩模的另一部分上形成第二金属层 并且在第一掩模层和第二金属层上形成第二掩模层。 然后，去除第一掩蔽层和包括覆盖第一掩模层的部分的第二掩蔽层的一部分，在第一和第二金属层的暴露于通过去除的步骤的部分上形成第三金属层 第一掩蔽层和第二掩蔽层的部分。 最后，第二掩模层，第二金属层; 除去除了第三金属层覆盖的部分之外的第一金属层。 以这种方式，可以节省用于集成各种无源元件的区域，并且可以减少包括集成电路和无源元件的半导体器件的总体面积。

    Ink jet print head and a method of producing the same
    7.
    发明授权
    Ink jet print head and a method of producing the same 失效
    喷墨打印头及其制造方法

    公开(公告)号：US06423241B1

    公开(公告)日：2002-07-23

    申请号：US09209560

    申请日：1998-12-11

    申请人： Jun Bo Yoon ,  Jae Duk Lee ,  Chul Hi Han ,  Choong Ki Kim ,  Doo Won Seo

    发明人： Jun Bo Yoon ,  Jae Duk Lee ,  Chul Hi Han ,  Choong Ki Kim ,  Doo Won Seo

    IPC分类号： G11B5127

    CPC分类号： B41J2/1626 ,  B41J2/1603 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1643

    摘要： Disclosed is an ink jet print head and a method of producing the same, the ink jet print head including a plurality of ink ejecting orifices which are formed with a desired shape and a uniform size by only once using metal plating technique, having an excellent productivity and a low manufacturing cost. According to a first embodiment of the present invention, in the steps for forming an improved metal barrier layer, which is comprised of the conventional barrier layer and the conventional nozzle plate combined together, the metal barrier layer can be formed on a wetting layer by using electrolytic plating or electroless plating of Ni. As a result, an upper surface of a first photoresist mold is completely covered with the overflowing Ni. Further, an upper portion of a second photoresist mold is partially covered with the overplating Ni and is partially opened at a proper size and a desired shape. Thereby, an ink ejecting orifice is created at the upper portion of the second photoresist mold. Alternatively, according to a second embodiment of the present invention, by forming a third photoresist mold at a predetermined position in which the ink ejecting orifice will be formed, the overflowing Ni is formed around the third photoresist mold, and thereby the ink ejecting orifice is created. The ink ejecting orifice has a desired shape, a uniform size and a high sectional height, which are adapted to provide an optimum ejection of the ink.

    摘要翻译： 公开了一种喷墨打印头及其制造方法，喷墨打印头包括多个喷墨孔，其通过仅使用一次金属镀覆技术形成具有期望形状和均匀尺寸的喷墨孔，具有优异的生产率 制造成本低。 根据本发明的第一实施例，在由常规阻挡层和常规喷嘴板组合在一起的形成改进的金属阻挡层的步骤中，金属阻挡层可以通过使用在润湿层上形成 Ni的电镀或化学镀。 结果，第一光致抗蚀剂模具的上表面被溢出的Ni完全覆盖。 此外，第二光致抗蚀剂模具的上部分被覆盖的Ni部分地覆盖，并且以适当的尺寸和期望的形状部分地打开。 由此，在第二光致抗蚀剂模具的上部形成喷墨口。 或者，根据本发明的第二实施例，通过在形成喷墨孔的预定位置形成第三光致抗蚀剂模具，在第三光致抗蚀剂模具周围形成溢流的Ni，从而喷墨口为 创建。 喷墨孔具有期望的形状，均匀的尺寸和高的截面高度，其适于提供油墨的最佳喷射。

    Method of fabricating a refractive silicon microlens
    8.
    发明授权
    Method of fabricating a refractive silicon microlens 失效
    制造折射硅微透镜的方法

    公开(公告)号：US06673252B2

    公开(公告)日：2004-01-06

    申请号：US09750135

    申请日：2000-12-29

    申请人： Choon Sup Lee ,  Chul Hi Han

    发明人： Choon Sup Lee ,  Chul Hi Han

    IPC分类号： B81C100

    CPC分类号： G02B3/0056 ,  G02B3/0012

    摘要： A method of fabricating a refractive silicon microlens by using micro-machining technology. The method of fabricating a refractive silicon microlens according to the present invention comprises the steps of forming a boron-doped region on a silicon substrate, and selectively removing regions of the substrate except for the boron-doped region to form a lens comprised of only the boron-doped region. With the method of the present invention, it is possible to fabricate a two-dimensional infrared silicon microlens array. By using such a two-dimensional infrared silicon microlens array in an infrared sensor, the detectivity of the infrared sensor can be increased by 3.4 times, which is the refraction index of silicon. In addition, the two-dimensional infrared silicon microlens array of the present invention can be used with commercial infrared telecommunication devices.

    摘要翻译： 使用微加工技术制造折射硅微透镜的方法。 根据本发明的制造折射硅微透镜的方法包括以下步骤：在硅衬底上形成硼掺杂区域，并且选择性去除除了掺杂硼的区域之外的衬底的区域以形成仅由 硼掺杂区域。 利用本发明的方法，可以制造二维红外硅微透镜阵列。 通过在红外线传感器中使用这种二维红外硅微透镜阵列，红外传感器的检测能力可以提高3.4倍，这是硅的折射率。 此外，本发明的二维红外硅微透镜阵列可以与商业红外线通信设备一起使用。

    Analog buffer and method of driving the same
    9.
    发明授权
    Analog buffer and method of driving the same 有权
    模拟缓冲器及其驱动方法

    公开(公告)号：US06801186B2

    公开(公告)日：2004-10-05

    申请号：US10097356

    申请日：2002-03-15

    申请人： Chul Hi Han ,  Hoon Ju Chung

    发明人： Chul Hi Han ,  Hoon Ju Chung

    IPC分类号： G09G336

    CPC分类号： G09G3/3688 ,  G11C27/024 ,  H03K5/003 ,  H03K5/023

    摘要： An analog buffer, and a driving method thereof, that has a low power consumption in driving a data line of a liquid crystal display and is insensitive to a deviation of device parameters to have a minor error between an input voltage and an output voltage, includes a first transistor and a second transistor connected in such a manner to be driven into a push-pull circuit. A first switch and a third switch connect and disconnect a first reference voltage and a second reference voltage such that the same current flows in the sources of the first and second transistors. A first capacitor charges the voltage between the gate and the source of the first transistor, and a second capacitor charges the voltage between the gate and the source of the second transistor. A second switch switches an application of the input voltage to the input stage of the push-pull circuit, and a fourth switch switches a charge of voltages between the gates and the sources of the first and second transistors in the first and second capacitors.

    摘要翻译： 一种模拟缓冲器及其驱动方法，其在驱动液晶显示器的数据线方面具有低功耗，并且对输入电压和输出电压之间具有较小误差的器件参数的偏差不敏感，包括 以这样的方式连接的第一晶体管和第二晶体管被驱动到推挽电路中。 第一开关和第三开关连接和断开第一参考电压和第二参考电压，使得相同的电流在第一和第二晶体管的源极中流动。 第一电容器对第一晶体管的栅极和源极之间的电压进行充电，并且第二电容器对第二晶体管的栅极和源极之间的电压进行充电。 第二开关将输入电压的施加切换到推挽电路的输入级，并且第四开关在第一和第二电容器中的第一和第二晶体管的栅极和源极之间切换电压。