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公开(公告)号：US07602635B2
公开(公告)日：2009-10-13
申请号：US11947092
申请日：2007-11-29
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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公开(公告)号：US07450413B2
公开(公告)日：2008-11-11
申请号：US11463917
申请日：2006-08-11
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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公开(公告)号：US07715222B2
公开(公告)日：2010-05-11
申请号：US12210712
申请日：2008-09-15
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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公开(公告)号：US20090141536A1
公开(公告)日：2009-06-04
申请号：US11947092
申请日：2007-11-29
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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公开(公告)号：US20080037313A1
公开(公告)日：2008-02-14
申请号：US11463917
申请日：2006-08-11
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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6.发明申请Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices 审中-公开电路设计结构和测量SRAM器件中阈值电压分布的方法公开(公告)号：US20090144677A1
公开(公告)日：2009-06-04
申请号：US11947180
申请日：2007-11-29
IPC分类号： G11C29/54
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50004 , G11C29/54
摘要： A design structure for a circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The design structure for the circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.
摘要翻译： 用于在线测试存储器件的电路的设计结构，其提供关于阈值电压变化的信息。 电路的设计结构包括具有一系列逆变器的环形振荡器阵列，其已经存在于存储器件中。 控制逻辑通过启用每个反相器并切换输入来系统地遍历所有环形振荡器。 平均频率及其分布被测量并记录在输出电路中。 从环形振荡器推导出存储器件中的阈值电压变化。 该电路还包括位于存储器件外部的两个反相器。 每个环形振荡器耦合到一个反相器。 逆变器预先调节环形振荡器的元件，以防止两个晶体管之间的电阻分压器。
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公开(公告)号：US20090010043A1
公开(公告)日：2009-01-08
申请号：US12210712
申请日：2008-09-15
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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8.发明授权Circuit and method to measure threshold voltage distributions in SRAM devices 有权测量SRAM器件中阈值电压分布的电路和方法公开(公告)号：US07352252B2
公开(公告)日：2008-04-01
申请号：US11456684
申请日：2006-07-11
CPC分类号： H03K3/0315 , G11C11/41 , G11C29/006 , G11C29/12 , G11C29/50 , G11C29/50004 , G11C2029/0403 , H01L22/34
摘要： A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.
摘要翻译： 用于存储器件的在线测试的电路，其提供关于阈值电压变化的信息。 该电路包括具有一系列逆变器的环形振荡器阵列，其已经存在于存储器件中。 控制逻辑通过启用每个反相器并切换输入来系统地遍历所有环形振荡器。 平均频率及其分布被测量并记录在输出电路中。 从环形振荡器推导出存储器件中的阈值电压变化。 该电路还包括位于存储器件外部的两个反相器。 每个环形振荡器耦合到一个反相器。 逆变器预先调节环形振荡器的元件，以防止两个晶体管之间的电阻分压器。
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9.发明申请Circuit And Method To Measure Threshold Voltage Distributions In Sram Devices 有权电路和方法来测量Sram器件中的阈值电压分布公开(公告)号：US20080024232A1
公开(公告)日：2008-01-31
申请号：US11456684
申请日：2006-07-11
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , G11C11/41 , G11C29/006 , G11C29/12 , G11C29/50 , G11C29/50004 , G11C2029/0403 , H01L22/34
摘要： A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.
摘要翻译： 用于存储器件的在线测试的电路，其提供关于阈值电压变化的信息。 该电路包括具有一系列逆变器的环形振荡器阵列，其已经存在于存储器件中。 控制逻辑通过启用每个反相器并切换输入来系统地遍历所有环形振荡器。 平均频率及其分布被测量并记录在输出电路中。 从环形振荡器推导出存储器件中的阈值电压变化。 该电路还包括位于存储器件外部的两个反相器。 每个环形振荡器耦合到一个反相器。 逆变器预先调节环形振荡器的元件，以防止两个晶体管之间的电阻分压器。
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公开(公告)号：US07480810B2
公开(公告)日：2009-01-20
申请号：US11276101
申请日：2006-02-14
CPC分类号： G06F1/28
摘要： Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The microprocessor includes an instruction sequencing unit and pipeline including a first series of instructions. A central voltage droop detection processor may be coupled to each of the voltage sensing circuits and the microprocessor. Voltage droop is detected using a voltage sensing circuit, after which processing of the microprocessor is interrupted. The pipeline may then be cleared. Subsequently, a second series of instructions including the first series of instructions, and additional instructions are issued. The additional instructions may include stall instructions that cause a delay in processing of the first series of instructions, which prevents re-occurrence of the voltage droop. The interruption and re-issuing also signals the microprocessor that all the data in a particular instruction stream might not be valid and allows recovery.
摘要翻译： 公开了用于从电压下降动态恢复的方法和系统。 在一个实施例中，提供耦合到多个电压感测电路的微处理器。 微处理器包括指令排序单元和包括第一系列指令的流水线。 中央电压下降检测处理器可以耦合到每个电压感测电路和微处理器。 使用电压检测电路检测电压下降，之后中断微处理器的处理。 然后可以清除管道。 随后，发出包括第一系列指令和附加指令的第二系列指令。 附加指令可以包括导致处理第一系列指令的延迟的停止指令，这防止电压下降的再次发生。 中断和重新发出也向微处理器指示特定指令流中的所有数据可能无效并允许恢复。
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