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1.发明授权Power reduction in a multiprocessor digital signal processor based on processor load 有权基于处理器负载的多处理器数字信号处理器的功耗降低
公开(公告)号：US6141762A
公开(公告)日：2000-10-31
申请号：US128030
申请日：1998-08-03
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/505 , G06F9/5094 , Y02B60/1217 , Y02B60/1285 , Y02B60/142 , Y02B60/144
摘要： Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.
摘要翻译： 多处理器芯片的改进操作通过动态地控制芯片的处理负载并且显着地大于开/关粒度来控制这些芯片的工作电压，从而最大限度地降低整体功耗来实现。 多处理器芯片中的控制器将各个处理器的任务分配给各个处理器之间的均衡，然后控制器将芯片上的时钟频率降至尽可能低的水平，同时确保正确的运行，并最终降低电源电压 。 通过控制多处理器芯片内的各个处理元件的电源电压以及控制多处理器芯片在其中运行的系统中的其它元件的电源电压，可以进一步改进。
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2.发明授权Method to transmit multiple data-streams of varying capacity data using virtual concatenation 有权使用虚拟级联传输不同容量数据的多个数据流的方法公开(公告)号：US08923337B2
公开(公告)日：2014-12-30
申请号：US13257272
申请日：2009-12-22
申请人： Kanwar Jit Singh
发明人： Kanwar Jit Singh
CPC分类号： H04L12/6418 , H04J3/1611 , H04J2203/0094
摘要： Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.
摘要翻译： 即时泄露是使用通过同步数字体系（SDH）网络的虚拟连接（VCAT）传输不同容量数据的多个数据流的方法，包括确定每个虚拟级联组（VCG）要请求的数据字节数的动作 聚合带宽的行时间并将其存储在VCG请求配置存储器中，从SDH帧的每个行时间顺序读取每个数据流的所请求数量的数据字节到行缓冲区，读取存储在 来自由一个或多个连接存储器确定的存储器地址的行缓冲器，其中连接存储器被编程为基于VCAT编号来执行行缓冲器的字节的排序，以及将路径开销（POH）和指针信息插入到读取的数据 在上一步的流中，使用VCAT通过SDH网络传输不同容量数据的多个数据流。
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公开(公告)号：US06438655B1
公开(公告)日：2002-08-20
申请号：US09437271
申请日：1999-11-10
IPC分类号： G06F1200
CPC分类号： G06F12/126
摘要： A cache implements bank-by-bank locking to keep critical code from being flushed out of the cache. A register is maintained to rank the banks from the most recently used to the least recently used. Ordinarily, when code needs to be moved into the cache, the least recently used bank is flushed, the code is moved into that bank, and the register is updated to identify that bank as the most recently used. However, if a bank is designated in a bypass vector as being locked, that bank is bypassed in the maintenance of the register and is thus never identified as the bank to be flushed.
摘要翻译： 缓存实现了逐行锁定，以使关键代码不被刷新出缓存。 维护一个注册表，将银行从最近使用的排列到最近使用的最少。 通常，当需要将代码移动到缓存中时，最近使用的最近使用的银行被刷新，代码被移动到该银行，并且更新注册表以将该银行标识为最近使用的银行。 然而，如果在旁路向导中指定一个银行被锁定，该银行在注册表的维护中被绕过，并且因此从未被识别为要刷新的银行。
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4.发明授权Method of and apparatus for efficiently debugging programs given limited system resources 失效给定有限的系统资源，有效地调试程序的方法和装置
公开(公告)号：US5794045A
公开(公告)日：1998-08-11
申请号：US769290
申请日：1996-12-18
CPC分类号： G06F11/3604
摘要： A device for creating and analyzing larger symbolic representations without the limitations imposed by available resources of previous devices is disclosed. More specifically, a debugger for debugging a symbolic representation of a program is disclosed. The debugger comprising means for inputting a set of characteristics, means for linking the set of characteristics to the symbolic representation, means for identifying a first portion of the symbolic representation mutually exclusive from the set of characteristics, and means for analyzing a second portion of the symbolic representation for the set of characteristics wherein the second portion being mutually exclusive from the first portion. A method of debugging programs using the debugger, in addition to the resultant debugged program, is also disclosed.
摘要翻译： 公开了一种用于创建和分析较大符号表示而不受先前设备的可用资源施加的限制的设备。 更具体地，公开了一种用于调试程序的符号表示的调试器。 调试器包括用于输入一组特征的装置，用于将特征集合与符号表示相关联的装置，用于识别与该特征集相互排斥的符号表示的第一部分的装置，以及用于分析该特征的第二部分的装置 所述特征集合的符号表示，其中所述第二部分与所述第一部分相互排斥。 还公开了使用调试器调试程序的方法，以及结果调试程序。
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5.发明申请METHOD TO TRANSMIT MULTIPLE DATA-STREAMS OF VARYING CAPACITY DATA USING VIRTUAL CONCATENATION 有权使用虚拟连接发送变化容量数据的多个数据流的方法公开(公告)号：US20120002682A1
公开(公告)日：2012-01-05
申请号：US13257272
申请日：2009-12-22
申请人： Kanwar Jit Singh
发明人： Kanwar Jit Singh
IPC分类号： H04L12/00
CPC分类号： H04L12/6418 , H04J3/1611 , H04J2203/0094
摘要： Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.
摘要翻译： 即时泄露是使用通过同步数字体系（SDH）网络的虚拟连接（VCAT）传输不同容量数据的多个数据流的方法，包括确定每个虚拟级联组（VCG）要请求的数据字节数的动作 聚合带宽的行时间并将其存储在VCG请求配置存储器中，从SDH帧的每个行时间顺序读取每个数据流的所请求数量的数据字节到行缓冲区，读取存储在 来自由一个或多个连接存储器确定的存储器地址的行缓冲器，其中连接存储器被编程为基于VCAT编号来执行行缓冲器的字节的排序，以及将路径开销（POH）和指针信息插入到读取的数据 在上一步的流中，使用VCAT通过SDH网络传输不同容量数据的多个数据流。
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6.发明申请公开(公告)号：US20080170571A1
公开(公告)日：2008-07-17
申请号：US11622699
申请日：2007-01-12
申请人： Dhiraj Kumar , Kanwar Jit Singh
发明人： Dhiraj Kumar , Kanwar Jit Singh
IPC分类号： H04L12/56
CPC分类号： H04L49/9047 , H04L49/3072 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A method and system for synchronous page addressing in a data packet switch is provided. Within the packet switch, separate devices are responsible for storing a portion of a received data packet, and thus a view of used memory addresses seen by one device matches that seen by the others. Each device uses the same order of memory addresses to write data so that bytes of data are stored as a linked-list of pages. Maintaining the same sequence of page requests and sequence of free-page addresses to which to write these pages ensures consistent addressing of the portions of the data packet.
摘要翻译： 提供了一种用于在数据分组交换机中同步寻址的方法和系统。 在分组交换机内，单独的设备负责存储接收到的数据分组的一部分，因此一个设备看到的已使用的存储器地址的视图与其他设备所看到的匹配。 每个设备使用相同的存储器地址顺序来写入数据，使得数据字节被存储为页面的链接列表。 维护相同的页面请求序列和自由页面地址序列来写入这些页面，确保数据包部分的一致寻址。
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公开(公告)号：US6078173A
公开(公告)日：2000-06-20
申请号：US629327
申请日：1996-04-08
摘要： A method for simultaneous testing of individual components in multiple three phase inverters, each connected to a common source of direct current electric power and being coupled to supply power to a respective one of a plurality of three phase loads, involves the steps of monitoring the voltage applied to the inverters and the current at each output phase terminal while gating each switching device in each inverter momentarily into conduction in sequence from a first switching device in a first phase to a last switching device in a third phase until an input voltage drop or an output current is detected. In response to a detected voltage drop, the sequence of gating is interrupted and advanced forward to the next occurring phase. If phase current is detected in any phase during gating, the inverter generating the current is disabled. The gating sequence is modified after detection of a voltage drop to initiate subsequent gating at a phase following the phase at which the voltage drop was detected to prevent inadvertent gating of short-circuited phases.
摘要翻译： 一种用于同时测试多个三相逆变器中的各个组件的方法，每个组件连接到公共的直流电源并被耦合以向多个三相负载中的相应的一个负载供电，包括以下步骤：监测电压 施加到逆变器和每个输出相端子处的电流，同时在每个逆变器中选通每个逆变器中的每个开关器件，从而从第一相中的第一开关器件到第三相中的最后一个开关器件依次导通，直到输入电压降或 检测出输出电流。 响应于检测到的电压降，门控序列被中断并且前进到下一个发生阶段。 如果在选通期间检测到任何相的相电流，则禁止产生电流的逆变器。 在检测到电压降之后修改门控序列，以在检测到电压降的相位之后的相位启动后续门控，以防止短路相的无意选通。
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