公开(公告)号：US06973096B2

公开(公告)日：2005-12-06

申请号：US09903334

申请日：2001-07-10

申请人： Christopher L. Chappell ,  Jeffrey D. Hoffman ,  Dmitrii A. Loukianov

发明人： Christopher L. Chappell ,  Jeffrey D. Hoffman ,  Dmitrii A. Loukianov

IPC分类号： H04L12/24 ,  H04L12/56 ,  H04J3/16 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： Disclosed are a system and method of processing upstream bandwidth allocation messages in a downstream management message received at a client termination device. Bandwidth allocation elements based upon selected ones of the bandwidth allocation messages are stored in a data buffer. The stored bandwidth allocation elements may be accessed from the buffer in response to a validation of a cyclic redundancy code in the downstream management message.

摘要翻译： 公开了一种在客户终端设备接收的下游管理消息中处理上行带宽分配消息的系统和方法。 基于选定的带宽分配消息的带宽分配元素存储在数据缓冲器中。 响应于下游管理消息中的循环冗余码的验证，可以从缓冲器访问所存储的带宽分配元素。

公开(公告)号：US20150382035A1

公开(公告)日：2015-12-31

申请号：US13996621

申请日：2011-12-21

申请人： Guoqing Li ,  Joseph A. Bennett ,  Gideon Prat ,  Solomon B. Trainin ,  Sang-Hee Lee ,  Vallabhajosyula Z. Somayazulu ,  George R. Hayek ,  Pat Brouillette ,  Dmitrii A. Loukianov

发明人： Guoqing Li ,  Joseph A. Bennett ,  Gideon Prat ,  Solomon B. Trainin ,  Sang-Hee Lee ,  Vallabhajosyula Z. Somayazulu ,  George R. Hayek ,  Pat Brouillette ,  Dmitrii A. Loukianov

IPC分类号： H04N21/242 ,  H04N21/61 ,  H04N21/43 ,  H04N21/236

CPC分类号： H04N21/242 ,  H04N21/23608 ,  H04N21/4305 ,  H04N21/6131

摘要： An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

摘要翻译： 提供了一种用于确定程序时钟参考（PCR）值有效性的方法，用于避免不准确的可变延迟引用（VDR）值，并且用于避免无线显示扩展的序列号和分组号之间的数据分组的不匹配。 该方法包括确定生成具有可选PCR值，VDR值和有效性指示符的数据分组载体。 该方法还可以涉及处理数据分组载波以确定数据分组载波是否具有任选的PCR值。 该方法还可以包括至少部分地至少部分地导致至少部分地基于来自数据分组载体的确定的不存在可选PCR值来生成替代PCR值。

公开(公告)号：US09723342B2

公开(公告)日：2017-08-01

申请号：US13996621

申请日：2011-12-21

申请人： Guoqing Li ,  Joseph A. Bennett ,  Gideon Prat ,  Solomon B. Trainin ,  Sang-Hee Lee ,  Vallabhajosyula Z. Somayazulu ,  George R. Hayek ,  Pat Brouillette ,  Dmitrii A. Loukianov

发明人： Guoqing Li ,  Joseph A. Bennett ,  Gideon Prat ,  Solomon B. Trainin ,  Sang-Hee Lee ,  Vallabhajosyula Z. Somayazulu ,  George R. Hayek ,  Pat Brouillette ,  Dmitrii A. Loukianov

IPC分类号： H04N21/242 ,  H04N21/236 ,  H04N21/61 ,  H04N21/43

CPC分类号： H04N21/242 ,  H04N21/23608 ,  H04N21/4305 ,  H04N21/6131

摘要： An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

公开(公告)号：US09225499B2

公开(公告)日：2015-12-29

申请号：US13976468

申请日：2012-03-28

申请人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

发明人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

IPC分类号： H04L5/14 ,  H04L1/00

CPC分类号： H04L5/14 ,  H04L1/0041 ,  H04L1/0083 ,  H04L12/2801 ,  H04L27/0002 ,  H04M11/00 ,  H04N21/6118 ,  H04N21/6168

摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

摘要翻译： 一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。 例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数 确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

公开(公告)号：US20130272357A1

公开(公告)日：2013-10-17

申请号：US13976468

申请日：2012-03-28

申请人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

发明人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

IPC分类号： H04L5/14

CPC分类号： H04L5/14 ,  H04L1/0041 ,  H04L1/0083 ,  H04L12/2801 ,  H04L27/0002 ,  H04M11/00 ,  H04N21/6118 ,  H04N21/6168

摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

摘要翻译： 一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。 例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数 确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。