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1.发明授权Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system 有权在数据处理系统的处理单元中的发布队列中发出与负载相关的指令公开(公告)号：US07991979B2
公开(公告)日：2011-08-02
申请号：US12236175
申请日：2008-09-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3838
摘要： A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to identifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
摘要翻译： 一种用于在处理单元中的发布队列中发布负载相关指令的系统和方法。 提供了一个加载缺失队列。 负载遗漏队列包括物理地址字段，发布队列位置字段，有效标识符字段，源标识符字段和数据类型字段。 调度丢失第一级缓存的加载指令，同时设置物理地址字段和数据类型字段。 识别负载相关的指令。 响应于识别负载相关指令，设置每个发布队列位置字段，有效标识符字段和源标识符字段。 如果问题队列位置字段引用了刷新指令，则清除有效的标识符字段。 加载指令被回收，确定有效标识符字段的值。 然后选择负载相关的指令用于在下一个处理周期中发出独立于负载相关指令的年龄。
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公开(公告)号：US20100250902A1
公开(公告)日：2010-09-30
申请号：US12410024
申请日：2009-03-24
IPC分类号： G06F9/312
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.
摘要翻译： 提供了一种跟踪取消分配的加载指令的机制。 处理器检测发送队列中的一组指令中的加载指令是否已经丢失。 响应于加载指令的未命中，指令调度器将加载指令分配给加载未命中队列，并从发出队列中释放加载指令。 指令调度器确定在依赖矩阵的发布队列部分中是否存在用于加载指令的依赖条目。 响应于依赖矩阵的发布队列部分中的加载指令的依赖条目的存在，指令调度器从依赖矩阵的发布队列部分的依赖条目读取数据，该依赖矩阵指定一组依赖的依赖指令 在加载指令中，将数据写入依赖矩阵的加载未命中队列部分中的新条目。
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3.发明申请System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit 审中-公开用于从处理单元中的问题队列中发出与负载相关的指令的系统和方法公开(公告)号：US20090113182A1
公开(公告)日：2009-04-30
申请号：US11923377
申请日：2007-10-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30094 , G06F9/3013 , G06F9/3824 , G06F9/384
摘要： A system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. In response to a LSU determining that a load request from a load instruction missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry corresponding to the load instruction. The LMQ associates at least one instruction dependent on the load request with the load-miss queue entry. Once data associated with the load request is retrieved, the LMQ selects at least one instruction dependent on the load request for execution on the next cycle. At least one instruction dependent on the load request is executed and a result is outputted.
摘要翻译： 一种用于从数据处理系统中的处理单元中的发布队列发出负载相关指令的系统和方法。 响应于LSU确定来自加载指令的加载请求错过了存储器层次结构中的第一级，LMQ分配与加载指令相对应的加载未命中队列条目。 LMQ将至少一个取决于负载请求的指令与负载丢失队列条目相关联。 一旦检索到与加载请求相关联的数据，则LMQ根据负载请求选择至少一个指令，以在下一个周期执行。 执行取决于负载请求的至少一个指令并输出结果。
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公开(公告)号：US08099582B2
公开(公告)日：2012-01-17
申请号：US12410024
申请日：2009-03-24
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.
摘要翻译： 提供了一种跟踪取消分配的加载指令的机制。 处理器检测发送队列中的一组指令中的加载指令是否已经丢失。 响应于加载指令的未命中，指令调度器将加载指令分配给加载缺省队列，并从发出队列中释放加载指令。 指令调度器确定在依赖矩阵的发布队列部分中是否存在用于加载指令的依赖条目。 响应于依赖矩阵的发布队列部分中的加载指令的依赖条目的存在，指令调度器从依赖矩阵的发布队列部分的依赖条目读取数据，该依赖矩阵指定一组依赖的依赖指令 在加载指令中，将数据写入依赖矩阵的加载未命中队列部分中的新条目。
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5.发明申请System and Method for Issuing Load-Dependent Instructions in an Issue Queue in a Processing Unit of a Data Processing System 有权用于在数据处理系统的处理单元中的问题队列中发出负载相关指令的系统和方法公开(公告)号：US20100077181A1
公开(公告)日：2010-03-25
申请号：US12236175
申请日：2008-09-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3838
摘要： A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to indentifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
摘要翻译： 一种用于在处理单元中的发布队列中发布负载相关指令的系统和方法。 提供了一个加载缺失队列。 负载遗漏队列包括物理地址字段，发布队列位置字段，有效标识符字段，源标识符字段和数据类型字段。 调度丢失第一级缓存的加载指令，同时设置物理地址字段和数据类型字段。 识别负载相关的指令。 响应于确定负载相关指令，设置每个发布队列位置字段，有效标识符字段和源标识符字段。 如果问题队列位置字段引用了刷新指令，则清除有效的标识符字段。 加载指令被回收，确定有效标识符字段的值。 然后选择负载相关的指令用于在下一个处理周期中发出独立于负载相关指令的年龄。
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6.发明授权Apparatus and method for implementing speculative clock gating of digital logic circuits 有权用于实现数字逻辑电路的推测时钟门控的装置和方法公开(公告)号：US07971161B2
公开(公告)日：2011-06-28
申请号：US12019718
申请日：2008-01-25
CPC分类号： G06F1/3203 , G06F1/10 , G06F1/3237 , Y02D10/128
摘要： A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
摘要翻译： 一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器的有效控制信号，有效控制 指示操作何时被第二流水线阶段n + 1执行的信号; 以及在第一流水线级中生成用于在第二流水线级中对多个附加寄存器门控时钟信号的推测有效控制信号，其中，仅使用总数的子集来产生推测有效控制信号 用于产生有效控制信号的控制输入，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器。
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公开(公告)号：US20100257341A1
公开(公告)日：2010-10-07
申请号：US12417801
申请日：2009-04-03
申请人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
发明人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell. A second read port couples to the first array and comprises a second read wordline and a second read bitline. The second read wordline couples to the second latch and the first column and asserts a second available signal based on the second bit. The second read bitline couples to the first row and generates a second ready signal based on the second read wordline and the first cell.
摘要翻译： 具有依赖矩阵的处理器包括第一阵列，其包括以多个列排列的多个单元和多个行。 每行表示处理器执行队列中的指令，每个单元表示处理器执行队列中的两个指令之间的依赖关系。 第一锁存器耦合到第一阵列并且包括第一位，第一位指示第一状态。 第二锁存器耦合到第一阵列并且包括第二位，第二位指示第二状态。 第一读取端口耦合到第一阵列，包括第一读取字线和第一读取位线。 第一读取字线耦合到第一锁存器和第一列，并基于第一位置位第一可用信号。 第一读取位线耦合到第一行并且基于第一可用信号和第一单元产生第一就绪信号。 第二读取端口耦合到第一阵列并且包括第二读取字线和第二读取位线。 第二读取字线耦合到第二锁存器和第一列，并基于第二位置位第二可用信号。 第二读取位线耦合到第一行，并且基于第二读取字线和第一单元产生第二就绪信号。
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公开(公告)号：US20100257339A1
公开(公告)日：2010-10-07
申请号：US12417831
申请日：2009-04-03
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell in the first array represents a dependency relationship between two instructions in the processor execution queue. A clear port couples to the first array and clears a column of the first array. A producer status module couples to the clear port and the first array and determines an execution status of a producer instruction, wherein the producer instruction is an instruction in the processor execution queue. An available-status port couples to the first array and the producer status module and sets a read wordline column corresponding to the producer instruction based on the execution status of the producer instruction. The available-status port deasserts the read wordline column in response to a selection of the producer for execution. The available-status port reasserts the read wordline column in the event the producer status module determines the producer instruction has been rejected. The clear port clears the column of the first array corresponding to the producer instruction in the event the producer status module determines the producer instruction has been executed.
摘要翻译： 具有依赖矩阵的处理器包括第一阵列，其包括以多个列排列的多个单元和多个行。 每行代表处理器执行队列中的指令，第一个数组中的每个单元表示处理器执行队列中的两个指令之间的依赖关系。 清除端口耦合到第一个数组，并清除第一个数组的列。 生产者状态模块耦合到清除端口和第一阵列，并且确定生成器指令的执行状态，其中生成器指令是处理器执行队列中的指令。 可用状态端口耦合到第一阵列和生成器状态模块，并且基于生成器指令的执行状态设置与生成器指令相对应的读字线列。 可用状态端口取消对读取的字线列的响应，以选择要执行的生产者。 在生产者状态模块确定生产者指令已被拒绝的情况下，可用状态端口重新发送读取字线列。 在生产者状态模块确定生产者指令已执行的情况下，清除端口清除与生产者指令对应的第一个阵列的列。
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9.发明申请APPARATUS AND METHOD FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS 有权实现数字逻辑电路的时钟调节的装置和方法公开(公告)号：US20090193281A1
公开(公告)日：2009-07-30
申请号：US12019718
申请日：2008-01-25
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/10 , G06F1/3237 , Y02D10/128
摘要： A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
摘要翻译： 一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器的有效控制信号，有效控制 指示操作何时被第二流水线阶段n + 1执行的信号; 以及在第一流水线级中生成用于在第二流水线级中对多个附加寄存器门控时钟信号的推测有效控制信号，其中，仅使用总数的子集来产生推测有效控制信号 用于产生有效控制信号的控制输入，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器。
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10.发明授权Structure for implementing speculative clock gating of digital logic circuits 失效用于实现数字逻辑电路的推测时钟门控的结构公开(公告)号：US08078999B2
公开(公告)日：2011-12-13
申请号：US12112063
申请日：2008-04-30
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register. The design structure includes a netlist describing the apparatus for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design.
摘要翻译： 体现在设计过程中使用的非暂时机器可读介质中的设计结构包括用于实现数字逻辑电路的推测时钟选通的装置，包括操作有效逻辑，其被配置为在第一流水线阶段n中生成有效的控制信号输入 指示第二流水线级n + 1中的第一寄存器，指示操作何时由第二流水线级n + 1执行的有效控制信号; 以及推测有效逻辑，其被配置为在所述第一流水线级中产生用于在第二流水线级中对多个附加寄存器门控时钟信号的推测有效控制信号，其中所述推测有效控制信号仅使用 用于产生有效控制信号的控制输入的总数，并且其中时钟信号被直接发送到第一寄存器。 该设计结构包括描述用于实现包括在多级管道设计中的数字逻辑电路的推测时钟门控的装置的网表。
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