摘要:
Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
摘要:
Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
摘要:
A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.
摘要:
A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.
摘要:
A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.
摘要:
A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.
摘要:
A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.
摘要:
A memory cell array, such as an EEPROM flash memory array, includes a current limiting circuit that limits a sum of leakage currents from nonselected memory cells during operation of the array, such as during a programming operation.
摘要:
A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.
摘要:
Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that is shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.