公开(公告)号：US08013581B2

公开(公告)日：2011-09-06

申请号：US12286384

申请日：2008-09-29

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: G05F1/00

CPC classification number: H02M3/33561 ,  H02J9/005 ,  H02M2001/0032 ,  Y02B70/16

Abstract: An exemplary power supply circuit configured for supply power for a load includes: a main power supply configured for converting received voltages into required direct current voltages; a microprocessor configured for providing control signals; a stand-by control circuit configured for controlling the main power supply; an energy storage circuit configured for supplying the stand-by control circuit. When the load stops operating, the microprocessor outputs a control signal to the stand-by control circuit, the stand-by control circuit outputs a corresponding control signal to turn off the main power supply. In response to when the load starts operating, the stand-by control circuit outputs a corresponding control signal to turn on the main power supply, and the main power supply charges the energy storage circuit.

Abstract translation: 配置为用于负载的电源的示例性电源电路包括：主电源，被配置为将接收的电压转换为所需的直流电压; 被配置为提供控制信号的微处理器; 备用控制电路，被配置为控制主电源; 配置为提供备用控制电路的能量存储电路。 当负载停止运行时，微处理器向待机控制电路输出控制信号，待机控制电路输出相应的控制信号，关闭主电源。 响应于负载开始运行时，待机控制电路输出相应的控制信号以接通主电源，并且主电源对能量存储电路充电。

公开(公告)号：US20110069419A1

公开(公告)日：2011-03-24

申请号：US12763152

申请日：2010-04-19

Applicant: XIAN-JUN SU ,  CHING-CHUNG LIN

Inventor： XIAN-JUN SU ,  CHING-CHUNG LIN

IPC: H02H9/00

CPC classification number: G02F1/136204

Abstract: An electrostatic discharge protection circuit includes an input terminal, a first diode, a second diode, a third diode, a fourth diode, a plurality of voltage stabilizer circuits, and a power terminal. The input terminal and the cathode of the second diode connect to the anode of the first diode; the voltage stabilizer circuits connect in parallel between the cathode of the first diode and the anode of the second diode. The power terminal connects to the anode of the third diode, the cathode of the third diode connects to the cathode of the first diode. The cathode of the fourth diode connects to ground, the anode of the fourth diode connects to the anode of the second diode.

Abstract translation: 静电放电保护电路包括输入端子，第一二极管，第二二极管，第三二极管，第四二极管，多个稳压电路和电源端子。 第二二极管的输入端子和阴极连接到第一二极管的阳极; 电压稳定器电路并联连接在第一二极管的阴极和第二二极管的阳极之间。 电源端子连接到第三个二极管的阳极，第三个二极管的阴极连接到第一个二极管的阴极。 第四二极管的阴极连接到地，第四二极管的阳极连接到第二二极管的阳极。

公开(公告)号：US20110019473A1

公开(公告)日：2011-01-27

申请号：US12898691

申请日：2010-10-05

Applicant: Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

Inventor： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

Abstract: An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.

Abstract translation: 本发明的一个实施例提供一种包括多个位线，多个存储单元和一个设备的存储器阵列。 多个存储单元中的每一个具有第一节点，第二节点和第三节点，其中第三节点耦合到多个位线之一。 该设备将多个位线耦合在一起以形成多个存储器单元之一的公共节点。

公开(公告)号：US20090225605A1

公开(公告)日：2009-09-10

申请号：US12423013

申请日：2009-04-14

Applicant: Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

Inventor： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C16/04 ,  G11C5/14

CPC classification number: G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

Abstract: A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

Abstract translation: NROM存储器件包括存储器单元阵列和第一和第二位线。 第一和第二位线耦合到存储器单元的相对侧。 在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。 还公开了可以容易地基于存储器单元的阈值电压分布来筛选边际存储器单元的方法。

公开(公告)号：US20090085655A1

公开(公告)日：2009-04-02

申请号：US12286384

申请日：2008-09-29

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: G05F1/10

CPC classification number: H02M3/33561 ,  H02J9/005 ,  H02M2001/0032 ,  Y02B70/16

Abstract: An exemplary power supply circuit configured for supply power for a load includes: a main power supply configured for converting received voltages into required direct current voltages; a microprocessor configured for providing control signals; a stand-by control circuit configured for controlling the main power supply; an energy storage circuit configured for supplying the stand-by control circuit. When the load stops operating, the microprocessor outputs a control signal to the stand-by control circuit, the stand-by control circuit outputs a corresponding control signal to turn off the main power supply. In response to when the load starts operating, the stand-by control circuit outputs a corresponding control signal to turn on the main power supply, and the main power supply charges the energy storage circuit.

Abstract translation: 配置为用于负载的电源的示例性电源电路包括：主电源，被配置为将接收的电压转换为所需的直流电压; 被配置为提供控制信号的微处理器; 备用控制电路，被配置为控制主电源; 配置为提供备用控制电路的能量存储电路。 当负载停止运行时，微处理器向待机控制电路输出控制信号，待机控制电路输出相应的控制信号，关闭主电源。 响应于负载开始运行时，待机控制电路输出相应的控制信号以接通主电源，并且主电源对能量存储电路充电。

公开(公告)号：US20070211540A1

公开(公告)日：2007-09-13

申请号：US11695668

申请日：2007-04-03

Applicant: Ching Chung Lin ,  Ken Chen ,  Nai Kuo ,  Han Chen ,  Chun Hung ,  Wen Hsieh

Inventor： Ching Chung Lin ,  Ken Chen ,  Nai Kuo ,  Han Chen ,  Chun Hung ,  Wen Hsieh

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/14

Abstract: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract translation: 虚拟氮化物只读存储器阵列具有氮化物只读存储器单元的矩阵，其中在擦除操作期间，氮化物只读存储器单元的非擦除侧连接到公共节点，以增强擦除均匀性 氮化物只读存储器阵列。 如果操作要求在氮化物只读存储单元的左侧擦除，则从内部电源向氮化物只读存储单元中的每一个向左侧提供正电压，并且对于每个 氮化物只读存储单元被放电到公共节点。 选择共模的电压足够高以防止穿通，同时足够低以保持用于擦除操作的横向电场最佳地起作用。

公开(公告)号：US20070086255A1

公开(公告)日：2007-04-19

申请号：US11250005

申请日：2005-10-13

Applicant: Ching-Chung Lin ,  Nai-Ping Kuo ,  Han-Sung Chen

Inventor： Ching-Chung Lin ,  Nai-Ping Kuo ,  Han-Sung Chen

IPC: G11C7/02

CPC classification number: G11C7/14 ,  G11C7/062 ,  G11C7/067 ,  G11C16/28

Abstract: In accordance with one embodiment of the invention, a memory device comprises an array of memory cells arranged into word lines and bit lines, with a sense amplifier and a plurality of reference cells for each bit line. The sense amplifier for a bit line compares the output of a memory cell for that bit line with the output of one of the plurality of reference cells for that bit line.

Abstract translation: 根据本发明的一个实施例，存储器件包括布置成字线和位线的存储器单元的阵列，具有读出放大器和用于每个位线的多个参考单元。 用于位线的读出放大器将该位线的存储器单元的输出与该位线的多个参考单元之一的输出进行比较。

公开(公告)号：US20060104113A1

公开(公告)日：2006-05-18

申请号：US11271300

申请日：2005-11-10

Applicant: Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

Inventor： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC: G11C16/06

CPC classification number: G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

Abstract: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

Abstract translation: 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US06251794B1

公开(公告)日：2001-06-26

申请号：US09252627

申请日：1999-02-18

Applicant: Chiang-Jen Peng ,  Ching-Chung Lin

Inventor： Chiang-Jen Peng ,  Ching-Chung Lin

IPC: H01L21302

CPC classification number: H01L21/02063 ,  H01L21/31133 ,  H01L21/31138 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01076 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A method for removing a photoresist layer from a semiconductor substrate following a conventional dry etching step. A first wet chemical treatment strips the photoresist. A second dry ash with oxygen plasma completes the photoresist removal. To assure complete removal of photoresist imbedded on or within the material underlying the photoresist film, the semiconductor substrate is preheat treated to a temperature in the range of 150 to 250 degrees Centigrade to release the photoresist prior to the second dry ash with oxygen plasma operation. In particular, this method eliminates photoresist extrusion defects from occurring during a bond pad alloy operation.

Abstract translation: 根据常规的干蚀刻步骤，从半导体衬底去除光致抗蚀剂层的方法。 第一次湿化学处理剥离光致抗蚀剂。 具有氧等离子体的第二干灰完成光致抗蚀剂的去除。 为了确保完全去除嵌入在光致抗蚀剂膜下面的材料上的光致抗蚀剂，将半导体衬底预热处理至150至250摄氏度的温度，以在第二干灰之前用氧等离子体操作释放光致抗蚀剂。 特别地，该方法消除了在焊垫合金操作期间发生的光致抗蚀剂挤出缺陷。

公开(公告)号：US20150042886A1

公开(公告)日：2015-02-12

申请号：US14450455

申请日：2014-08-04

Applicant: CHING-CHUNG LIN

Inventor： CHING-CHUNG LIN

IPC: H04N5/268

CPC classification number: H04N21/4135 ,  H04N5/765 ,  H04N21/4104

Abstract: An electronic device connected with numerous first load medias and numerous second load medias. The electronic device comprises a processor and a switch module. The processor is capable of switching between a first working mode and a second working mode. Under the second working mode, the processor generates a second control signal, the switch mode establishes independent electronic connections between a specified first load media and all of the second load medias, thus, the specified first load media simultaneously connects and communicates with all of the second load medias.

Abstract translation: 与许多第一负载介质和许多第二负载介质连接的电子设备。 电子设备包括处理器和开关模块。 处理器能够在第一工作模式和第二工作模式之间切换。 在第二工作模式下，处理器产生第二控制信号，开关模式在指定的第一负载介质和所有第二负载介质之间建立独立的电子连接，因此，指定的第一负载介质同时连接并与所有的 第二负载媒体。