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    Low power high speed program method for multi-time programmable memory device
    2.
    发明授权
    Low power high speed program method for multi-time programmable memory device 有权
    低功耗高速编程方法，用于多时间可编程存储器件

    公开(公告)号：US09543016B1

    公开(公告)日：2017-01-10

    申请号：US14869820

    申请日：2015-09-29

    申请人： Integrated Silicon Solution, Inc.

    发明人： Kyoung Chon Jin

    IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    CPC分类号： G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30 ,  G11C16/345 ,  G11C16/3459 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/7884

    摘要： A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

    摘要翻译： 用于PMOS多时间可编程（MTP）闪存器件的编程方法将选择栅极晶体管偏置到恒定的漏极电流电平，并将控制栅极偏置电压从低电压电平扫描到高电压电平，同时保持电池电流周围 预定的电池电流限制电平。 以这种方式，PMOS MTP闪存器件可以使用热载流子注入（HCI）实现低功率和高速程序。 本发明的编程方法能够实现PMOS MTP闪存单元的多位编程，从而提高编程速度，同时保持低功耗。

    ADAPTIVE ERASE METHODS FOR NON-VOLATILE MEMORY
    4.
    发明申请
    ADAPTIVE ERASE METHODS FOR NON-VOLATILE MEMORY 有权
    用于非易失性存储器的自适应擦除方法

    公开(公告)号：US20150117112A1

    公开(公告)日：2015-04-30

    申请号：US14069195

    申请日：2013-10-31

    申请人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

    发明人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

    IPC分类号： G11C16/16 ,  G11C16/34

    CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

    摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

    摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

    Block and page level bad bit line and bits screening methods for program algorithm
    5.
    发明授权
    Block and page level bad bit line and bits screening methods for program algorithm 有权
    块和页级坏位线和位筛选方法的程序算法

    公开(公告)号：US08880964B2

    公开(公告)日：2014-11-04

    申请号：US13622765

    申请日：2012-09-19

    申请人： SanDisk Technologies Inc.

    发明人： Jun Wan ,  Bo Lei ,  Feng Pan ,  Yongke Sun

    IPC分类号： G11C29/00 ,  G11C16/34

    CPC分类号： G11C16/349 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3459 ,  G11C29/025 ,  G11C29/44 ,  G11C2029/1204

    摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.

    摘要翻译： 编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。 可以存储识别有缺陷的NAND串的状态位。 要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。 例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。 随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的比特翻转回其原始值。 在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

    Data storage in analog memory cell arrays having erase failures
    6.
    发明授权
    Data storage in analog memory cell arrays having erase failures 有权
    具有擦除故障的模拟存储单元阵列中的数据存储

    公开(公告)号：US08527819B2

    公开(公告)日：2013-09-03

    申请号：US12677114

    申请日：2008-10-12

    申请人： Ofir Shalvi ,  Shai Winter ,  Naftali Sommer ,  Dotan Sokolov

    发明人： Ofir Shalvi ,  Shai Winter ,  Naftali Sommer ,  Dotan Sokolov

    IPC分类号： G11C29/00

    CPC分类号： G11C16/344 ,  G11C16/04 ,  G11C16/345 ,  G11C29/52

    摘要： A method for data storage includes performing an erasure operation on a group of analog memory cells (32). One or more of the memory cells in the group, which failed the erasure operation, are identified as erase-failed cells. A storage configuration that is used for programming the analog memory cells in the group is modified responsively to the identified erase-failed cells. Data is stored in the group of the analog memory cells using the modified storage configuration.

    摘要翻译： 一种用于数据存储的方法包括对一组模拟存储器单元（32）执行擦除操作。 组中的一个或多个存储器单元，其在擦除操作中失败，被识别为擦除故障单元。 用于对组中的模拟存储器单元进行编程的存储配置响应于所识别的擦除故障单元被修改。 使用修改的存储配置将数据存储在模拟存储器单元的组中。

    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    半导体存储器件及其工作方法

    公开(公告)号：US20120327718A1

    公开(公告)日：2012-12-27

    申请号：US13531998

    申请日：2012-06-25

    申请人： Hyung Min LEE

    发明人： Hyung Min LEE

    IPC分类号： G11C16/10

    CPC分类号： G11C16/06 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/345

    摘要： An operating method of a semiconductor memory device includes performing a first LSB program loop for storing first LSB data in first memory cells of a word line, performing a second LSB program loop for storing second LSB data in second memory cells of the selected word line and for detecting over-erased memory cells having threshold voltages lower than an over-erase reference voltage of a negative potential to raise the threshold voltages to be higher than the over-erase reference voltage, performing a first MSB program loop for storing first MSB data in the first memory cells, and performing a second MSB program loop for storing second MSB data in the second memory cells.

    摘要翻译： 半导体存储器件的操作方法包括：执行第一LSB程序循环，用于将第一LSB数据存储在字线的第一存储单元中，执行用于将第二LSB数据存储在所选字线的第二存储器单元中的第二LSB程序循环;以及 用于检测具有低于负电位的过擦除参考电压的阈值电压的过擦除存储器单元，以将阈值电压升高到高于过擦除参考电压，执行用于存储第一MSB数据的第一MSB程序循环 第一存储器单元，并且执行用于在第二存储器单元中存储第二MSB数据的第二MSB程序循环。

    Method and Apparatus for the Erase Suspend Operation
    8.
    发明申请
    Method and Apparatus for the Erase Suspend Operation 有权
    擦除挂起操作的方法和装置

    公开(公告)号：US20120057410A1

    公开(公告)日：2012-03-08

    申请号：US12875003

    申请日：2010-09-02

    申请人： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

    发明人： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/345 ,  G11C16/3454

    摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

    摘要翻译： 非易失性存储器的各个方面具有改进的擦除暂停过程。 偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。 结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

    Nonvolatile Semiconductor Memory Device
    9.
    发明申请
    Nonvolatile Semiconductor Memory Device 有权
    非易失性半导体存储器件

    公开(公告)号：US20110267886A1

    公开(公告)日：2011-11-03

    申请号：US13179714

    申请日：2011-07-11

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Nonvolatile semiconductor memory device
    10.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07746707B2

    公开(公告)日：2010-06-29

    申请号：US11929210

    申请日：2007-10-30

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选择的存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。