公开(公告)号：US07304875B1

公开(公告)日：2007-12-04

申请号：US11184414

申请日：2005-07-19

申请人： Chuen Der Lien ,  Michael Miller ,  Chau-Chin Wu ,  Kee Park ,  Scott Yu-Fan Chu

发明人： Chuen Der Lien ,  Michael Miller ,  Chau-Chin Wu ,  Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G06F11/1064 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/816 ,  G11C2029/1208

摘要： Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in self repair (BISR) of hard memory defects and/or compare logic defects in the plurality of CAM array blocks concurrently with operations to search entries in the plurality of CAM array blocks.

摘要翻译： 搜索引擎设备包括其中具有多个CAM阵列块的内容可寻址存储器（CAM）核和控制电路。 电耦合到多个CAM阵列块的控制电路被配置为与搜索操作同时执行硬存储器缺陷的内置自修复（BISR）和/或比较多个CAM阵列块中的逻辑缺陷 多个CAM阵列块中的条目。

公开(公告)号：US07050317B1

公开(公告)日：2006-05-23

申请号：US10927453

申请日：2004-08-26

申请人： Chuen-Der Lien ,  Kee Park ,  Scott Yu-Fan Chu

发明人： Chuen-Der Lien ,  Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： Content addressable memory (CAM) devices include at least one CAM array having a plurality of columns of ternary CAM cells therein. A bit/data line driver circuit, which receives search words and write words, is electrically coupled to the CAM array. The bit/data line driver circuit is configured to save power by logically combining incoming search words with a global mask that designates locations of active ones of the plurality of columns having exclusively locally masked CAM cells at valid entries therein. The bit/data line driver circuit includes a global mask generator configured to receive write words to be added to the CAM array during respective write operations.

摘要翻译： 内容可寻址存储器（CAM）设备包括其中具有多列三元CAM单元的至少一个CAM阵列。 接收搜索字和写入字的位/数据线驱动电路电耦合到CAM阵列。 位/数据线驱动器电路被配置为通过逻辑地组合传入的搜索词与通过在其中的有效条目中指定了具有本地掩蔽的CAM单元的多个列中的活动的列的位置的全局掩码来节省功率。 位/数据线驱动器电路包括全局掩模生成器，其被配置为在各个写入操作期间接收要添加到CAM阵列的写入字。

公开(公告)号：US06775168B1

公开(公告)日：2004-08-10

申请号：US10622408

申请日：2003-07-18

申请人： Kee Park ,  Scott Yu-Fan Chu

发明人： Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C1500

CPC分类号： G11C15/00

摘要： Content addressable memory (CAM) devices include a first match line segment associated with a first row of CAM cells within a CAM array and an inverter having an input electrically coupled to the first match line segment. A match line precharge support circuit is provided. The match line precharge support circuit includes a first PMOS transistor having a gate terminal electrically coupled to an output of the inverter, a first current carrying terminal that is electrically coupled to the first match line segment and a second current carrying terminal that is electrically coupled to a power supply line.

摘要翻译： 内容可寻址存储器（CAM）设备包括与CAM阵列内的第一行CAM单元相关联的第一匹配线段和具有电耦合到第一匹配线段的输入的反相器。 提供了匹配线预充电支持电路。 匹配线预充电支持电路包括具有电耦合到反相器的输出的栅极端子的第一PMOS晶体管，电耦合到第一匹配线段的第一载流端子和电耦合到 电源线。

公开(公告)号：US07669005B1

公开(公告)日：2010-02-23

申请号：US10613542

申请日：2003-07-03

申请人： Kee Park ,  Robert J. Proebsting ,  Scott Yu-Fan Chu ,  Michael Miller ,  Mark Baumann

发明人： Kee Park ,  Robert J. Proebsting ,  Scott Yu-Fan Chu ,  Michael Miller ,  Mark Baumann

IPC分类号： G06F12/00

CPC分类号： G11C15/00 ,  H04L45/742

摘要： Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.

摘要翻译： 内容可寻址存储器（CAM）设备使用硬和软优先级技术来分配不同优先级的条目。 CAM设备内的多个CAM阵列块的优先级可以在条目加载之前被编程，也可以在操作期间被重新编程，因为CAM设备内的条目的分配改变。 条目的分配可能会随着条目的添加或删除而变化，或者条目被重新设定为优先级。 CAM设备包括优选的优先级分辨率电路，其可以解决响应于搜索操作而产生的多个命中信号之间的竞争的软和硬优先级。 这种命中信号可以是有效的，以反映CAM阵列块内至少一个匹配条目的存在。 可以使用哪个主动命中信号具有最高总体优先级的分辨率在许多之中，以便于识别整个CAM设备内的最高优先级匹配条目的位置（例如，阵列地址和行地址）。 优先级分辨率电路还可以解决具有相同软优先级的两个或更多个激活命中信号之间的竞争硬优先级。 提供优先级分辨率电路的这个方面，使得每当具有相同软优先级的每个CAM阵列块在搜索操作期间被检测为具有匹配条目时，可以解决具有最高总优先级的主动命中信号。

公开(公告)号：US06937491B2

公开(公告)日：2005-08-30

申请号：US10263223

申请日：2002-10-02

申请人： Kee Park ,  Scott Yu-Fan Chu

发明人： Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.

摘要翻译： 内容可寻址存储器（CAM）设备使用硬和软优先级技术来分配不同优先级的条目。 CAM设备内的多个CAM阵列块的优先级可以在条目加载之前被编程，也可以在操作期间被重新编程，因为CAM设备内的条目的分配改变。 条目的分配可能会随着条目的添加或删除而变化，或者条目被重新设定为优先级。 CAM设备包括优选的优先级分辨率电路，其可以解决响应于搜索操作而产生的多个命中信号之间的竞争的软和硬优先级。 这种命中信号可以是有效的，以反映CAM阵列块内至少一个匹配条目的存在。 可以使用哪个主动命中信号具有最高总体优先级的分辨率在许多之中，以便于识别整个CAM设备内的最高优先级匹配条目的位置（例如，阵列地址和行地址）。 优先级分辨率电路还可以解决具有相同软优先级的两个或更多个激活命中信号之间的竞争硬优先级。 提供优先级分辨率电路的这个方面，使得每当具有相同软优先级的每个CAM阵列块在搜索操作期间被检测为具有匹配条目时，可以解决具有最高总优先级的主动命中信号。

公开(公告)号：US06879532B1

公开(公告)日：2005-04-12

申请号：US10934209

申请日：2004-09-03

申请人： Robert J. Proebsting ,  Scott Yu-Fan Chu ,  Kee Park

发明人： Robert J. Proebsting ,  Scott Yu-Fan Chu ,  Kee Park

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C15/00

摘要： Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.

摘要翻译： 内容可寻址存储器（CAM）设备包括至少一个CAM阵列，其被配置为通过执行通过初始漂移多个的至少一些来暂时保持位线功率的分级比较操作来识别新的搜索词与其中的条目之间的至少一个匹配 并且然后响应于检测到新搜索词的第一位与所述新搜索词中的条目之间的至少一个部分匹配而在新搜索词的第二位中驱动多个位线中的至少一些位线 CAM阵列。

公开(公告)号：US07193876B1

公开(公告)日：2007-03-20

申请号：US11181534

申请日：2005-07-14

申请人： Kee Park ,  Scott Yu-Fan Chu

发明人： Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G11C15/04 ,  G11C29/52

摘要： A CAM array has at least one row therein containing a plurality of memory cells with different susceptibilities to soft errors. The memory cells having reduced susceptibilities to soft errors include those used in check bit cells and/or CAM cells containing valid bit data and/or force no-hit data. Additional memory cells may also be provided with somewhat greater susceptibilities to soft errors and somewhat more aggressive design rules (e.g., smaller layout area). These additional memory cells may include those used in ternary CAM cells (e.g., XY CAM cells) within the row.

摘要翻译： CAM阵列具有至少一行，其中包含对软错误具有不同敏感度的多个存储单元。 具有降低的软错误敏感性的存储器单元包括在包含有效位数据和/或强制无命中数据的校验位单元和/或CAM单元中使用的存储单元。 另外的存储器单元还可以具有对软错误和稍微更激进的设计规则（例如，更小的布局区域）的更高的敏感度。 这些附加存储器单元可以包括在行内的三元CAM单元（例如，XY CAM单元）中使用的那些。

公开(公告)号：US06987684B1

公开(公告)日：2006-01-17

申请号：US10738264

申请日：2003-12-17

申请人： Kenneth Branth ,  Kee Park ,  Scott Yu-Fan Chu ,  Thomas Diede

发明人： Kenneth Branth ,  Kee Park ,  Scott Yu-Fan Chu ,  Thomas Diede

IPC分类号： G11C15/00

CPC分类号： G06F11/1064

摘要： Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit that is electrically coupled to the CAM core. The control circuit is configured to support internal error detection and correction operations using modified Hamming code words. These operations are performed without significant impact on the compare bandwidth of the search engine device, even when operations to read entries from the CAM core are performed as foreground operations that may block concurrent search operations. The control circuit may perform the error detection and correction operations by issuing multiple read instructions. These instructions include a first instruction (e.g., error check instruction) to read at least a first entry into the CAM core for the purpose of error detection and then, in response to detecting the first entry as erroneous, issuing a second instruction to read the first entry from the CAM core. The entry is then corrected and written back into the CAM core.

摘要翻译： 搜索引擎设备包括其中具有多个CAM阵列块的内容可寻址存储器（CAM）核心和与CAM内核电连接的控制电路。 控制电路被配置为使用改进的汉明码字来支持内部错误检测和校正操作。 即使执行从CAM核心读取条目的操作被执行作为可能阻止并发搜索操作的前台操作，这些操作也不会对搜索引擎设备的比较带宽产生重大影响。 控制电路可以通过发出多个读取指令来执行错误检测和校正操作。 这些指令包括第一指令（例如，错误检查指令），用于为了错误检测的目的读取至少一个到CAM内核的第一条目，然后响应于检测到第一条目是错误的，发出第二条指令来读取 首先从CAM核心进入。 然后将条目更正并写入CAM内核。

公开(公告)号：US06965519B1

公开(公告)日：2005-11-15

申请号：US10464598

申请日：2003-06-18

申请人： Kee Park ,  Scott Yu-Fan Chu

发明人： Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04 ,  G11C15/00

摘要： Segmented CAM arrays are provided with dual-capture match line signal repeaters that support high speed pipelined search operations. A dual-capture match line signal repeater may extend between xR and xS segments of CAM cells within a respective row. This repeater provides high speed operation by quickly accessing the state (match or miss) of a match line segment when a corresponding segment of CAM cells connected to the match line segment undergo a respective stage of a pipelined search operation. If the match line segment is initially assessed as having a match signal thereon, then that match signal is passed to a next higher match line segment within the same row and a next stage search operation is commenced. However, if the match line segment is erroneously assessed as having a match signal thereon, when a miss condition was actually present in the corresponding segment of CAM cells, then the signal repeater will operate to capture a late miss signal and pass that late miss signal to the next higher match line segment to correct an error.

摘要翻译： 分段CAM阵列提供双捕获匹配线路信号中继器，支持高速流水线搜索操作。 双捕获匹配线信号中继器可以在相应行内的CAM单元的xR和xS段之间延伸。 当连接到匹配线段的CAM单元的相应段经历流水线搜索操作的相应阶段时，该中继器通过快速访问匹配线段的状态（匹配或未命中）来提供高速操作。 如果匹配线段最初被评估为具有匹配信号，则该匹配信号被传递到同一行内的下一较高匹配线段，并且开始下一级搜索操作。 然而，如果匹配线段被错误地评估为具有匹配信号，则当CAM单元的对应段中实际存在未命中条件时，信号中继器将操作以捕获延迟的未命中信号并将该延迟的未命中信号 到下一个较高的匹配线段来纠正错误。

公开(公告)号：US06829153B1

公开(公告)日：2004-12-07

申请号：US10622396

申请日：2003-07-18

申请人： Kee Park ,  Scott Yu-Fan Chu

发明人： Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C1500

CPC分类号： G11C15/00

摘要： Content addressable memory (CAM) devices according to embodiments of the present invention conserve match line and bit line power when CAM array blocks therein are searched. These CAM array blocks are searched in a pipelined segment-to-segment manner to increase search speed. The pipelined search operations may also be interleaved with write and read operations in an efficient manner that reduces the occurrence of pipeline bubbles.

摘要翻译： 根据本发明的实施例的内容可寻址存储器（CAM）设备在搜索CAM阵列块时保存匹配线和位线功率。 这些CAM阵列块以流水线段到段的方式进行搜索，以提高搜索速度。 流水线搜索操作还可以以有效的方式与写入和读取操作交错，从而减少管道气泡的发生。