公开(公告)号：US20060186947A1

公开(公告)日：2006-08-24

申请号：US11064920

申请日：2005-02-24

申请人： Yung Lin ,  Yu Lin ,  Roger Chen ,  Chun Hung

发明人： Yung Lin ,  Yu Lin ,  Roger Chen ,  Chun Hung

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A multimode charge pump circuit has a single charge pump that is responsive to a set of clock signals. The set of clock signals is provided in a first mode with a variable frequency according to a first function of the supply potential and temperature, and in a second mode with a variable frequency according to a second function of the supply potential and temperature. Circuitry configures all of the plurality of stages in series during the first mode in order to produce a higher voltage output, and configures a subset of the plurality of stages in series, while disabling the other stages, during the second mode in order to produce a lower voltage output. A precharge circuit is provided that operates as a supply node in the second mode, and as a precharge/clamp in the first mode.

公开(公告)号：US20070121386A1

公开(公告)日：2007-05-31

申请号：US11624612

申请日：2007-01-18

申请人： Wen Chiao Ho ,  Chin Chang ,  Kuen Chang ,  Chun Hung

发明人： Wen Chiao Ho ,  Chin Chang ,  Kuen Chang ,  Chun Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3459

摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level1).

摘要翻译： 本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在 读取窗口由互补位干扰引起。 在第一实施例中，本发明以具有四位的多位单元按以下顺序对多电平单元进行编程：编程第三程序电平（电平3），编程第一程序电平（电平1）和 第二程序级（级别2）到级别1，并且从第一程序级编程第二程序级。 在第二实施例中，本发明按照以下顺序对具有四位的多位单元中的多电平单元进行编程：编程第三程序电平（级别3），编程第二程序电平（级别2），以及 编程第一个程序级（1级）。

公开(公告)号：US20070211540A1

公开(公告)日：2007-09-13

申请号：US11695668

申请日：2007-04-03

申请人： Ching Chung Lin ,  Ken Chen ,  Nai Kuo ,  Han Chen ,  Chun Hung ,  Wen Hsieh

发明人： Ching Chung Lin ,  Ken Chen ,  Nai Kuo ,  Han Chen ,  Chun Hung ,  Wen Hsieh

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/14

摘要： A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

摘要翻译： 虚拟氮化物只读存储器阵列具有氮化物只读存储器单元的矩阵，其中在擦除操作期间，氮化物只读存储器单元的非擦除侧连接到公共节点，以增强擦除均匀性 氮化物只读存储器阵列。 如果操作要求在氮化物只读存储单元的左侧擦除，则从内部电源向氮化物只读存储单元中的每一个向左侧提供正电压，并且对于每个 氮化物只读存储单元被放电到公共节点。 选择共模的电压足够高以防止穿通，同时足够低以保持用于擦除操作的横向电场最佳地起作用。

公开(公告)号：US20070069800A1

公开(公告)日：2007-03-29

申请号：US11233901

申请日：2005-09-23

申请人： Yi-Chun Shih ,  Chun Hung ,  Kuen-Long Chang ,  Chuan-Ying Yu

发明人： Yi-Chun Shih ,  Chun Hung ,  Kuen-Long Chang ,  Chuan-Ying Yu

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2003/071

摘要： A negative charge-pump circuit for flash memory includes a well, a pass-gate transistor, a well bias circuit and a negative voltage recovery circuit. The pass-gate transistor has a source, a drain and a gate. The well bias circuit controls the well to remain one of zero biased and reverse biased. The negative voltage recovery circuit is coupled to a negative recovery voltage and coupled to the pass-gate transistor to selectively provide the negative recovery voltage to the pass-gate transistor when the charge-pump circuit is disabled.

摘要翻译： 用于闪速存储器的负电荷泵电路包括阱，通栅晶体管，阱偏置电路和负电压恢复电路。 栅极晶体管具有源极，漏极和栅极。 阱偏置电路控制阱保持零偏置和反向偏置之一。 负电压恢复电路耦合到负恢复电压并且耦合到通栅晶体管，以在电荷泵电路被禁用时选择性地向通过栅极晶体管提供负恢复电压。

公开(公告)号：US20070053225A1

公开(公告)日：2007-03-08

申请号：US11210425

申请日：2005-08-24

申请人： Ching Lin ,  Ken Chen ,  Nai Kuo ,  Han Chen ,  Chun Hung ,  Wen Hsieh

发明人： Ching Lin ,  Ken Chen ,  Nai Kuo ,  Han Chen ,  Chun Hung ,  Wen Hsieh

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/14

摘要： A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally. In an alternative embodiment, non-erasing sides of NROM cells in the NROM array are connected to a current source during an erase operation for enhancing the erase uniformity of the NROM array. If an operation requests erasing the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a current source. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the current source.

摘要翻译： 虚拟接地NROM阵列具有NROM单元的矩阵，其中在擦除操作期间，NROM单元的非擦除侧连接到公共节点，以增强NROM阵列的擦除均匀性。 如果操作请求在NROM单元的左侧擦除，则对于NROM单元中的每一个，从内部电源向左侧提供正电压，并且将NROM单元中的每一个的右侧放电到公共节点 。 如果操作请求擦除NROM单元的右侧，则对于每个NROM单元，从内部电源向右侧提供正电压，并且每个NROM单元的右侧连接到公共节点。 选择共模的电压足够高以防止穿通，同时足够低以保持用于擦除操作的横向电场最佳地起作用。 在替代实施例中，在擦除操作期间，NROM阵列中的NROM单元的不擦除侧连接到电流源，以增强NROM阵列的擦除均匀性。 如果操作请求擦除NROM单元的左侧，则从NROM单元的每一个的内部电源向左侧提供正电压，并且将NROM单元中的每一个的右侧放电到电流源。 如果操作请求擦除NROM单元的右侧，则从NROM单元的每一个向内部电源向右侧提供正电压，并且每个NROM单元的右侧连接到电流源。

公开(公告)号：US20060016232A1

公开(公告)日：2006-01-26

申请号：US11178817

申请日：2005-07-11

申请人： Chun Hung

发明人： Chun Hung

IPC分类号： E05B27/08 ,  E05B29/04

CPC分类号： E05B35/086 ,  E05B27/0032 ,  E05B27/0053 ,  E05B27/083 ,  E05B31/00 ,  Y10S70/63 ,  Y10T70/7458 ,  Y10T70/7565 ,  Y10T70/7593 ,  Y10T70/7599 ,  Y10T70/7768 ,  Y10T70/7802 ,  Y10T70/8622

摘要： A locking device, which mounts a user key (the first key) and a manager key (the second key) separatedly, places a first lock and a second lock unitedly in an outer cylinder. The first lock is opened or rotated by the first key. After the first lock is open, the first key cannot be pulled out of the locking device. If the second lock is open by the second key, the first key can be pulled out together with the second key.

摘要翻译： 分别安装用户键（第一键）和管理键（第二键）的锁定装置将第一锁和第二锁整合在外筒中。 第一个锁由第一个键打开或旋转。 第一个锁打开后，第一个键不能被拉出锁定装置。 如果通过第二个键打开第二个锁，则第一个键可以与第二个键一起拉出。