公开(公告)号：US08065593B2

公开(公告)日：2011-11-22

申请号：US12781749

申请日：2010-05-17

Applicant: Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

Inventor： Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

IPC: H03M13/00

CPC classification number: H03M13/2936 ,  H03M13/2732 ,  H03M13/293

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract translation: 提供了一种擦除辅助块代码解码器及相关方法。 擦除辅助块码解码器包括第一块解码器，擦除处理器和第二块码解码器。 第一块解码器，例如Reed-Solomon解码器，被配置为对先前受突发错误影响的诸如字节的数据元素块进行解码。 第一块解码器还被配置为识别其不能解码的这些块的那些。 擦除处理器被配置为通过在擦除识别处理中利用由第一块解码器校正的解码块中的数据元素来识别不可解码块中的数据元素作为擦除。 第二块解码器，例如相同或不同的里德 - 所罗门解码器，被配置为通过在解码中利用由擦除处理器识别的擦除来解码一个或多个不可解码块。

公开(公告)号：US20140029706A1

公开(公告)日：2014-01-30

申请号：US13560095

申请日：2012-07-27

Applicant: Fu-Hsuan Chiu ,  Chun-Hsuan Kuo

Inventor： Fu-Hsuan Chiu ,  Chun-Hsuan Kuo

IPC: H04B1/10

CPC classification number: H04B1/71075 ,  H04B1/71055 ,  H04B1/71072

Abstract: In one embodiment, interference suppression is improved by improving convergence criteria. For some embodiments, convergence is improved by employing non-constant alpha-beta-weighting. For other embodiments, convergence is improved by employing successive interference suppression methods that have guaranteed convergence properties.

Abstract translation: 在一个实施例中，通过改进收敛标准来改善干扰抑制。 对于一些实施例，通过使用非常数α-β加权来提高收敛。 对于其他实施例，通过采用具有保证的收敛特性的连续的干扰抑制方法来提高收敛。

公开(公告)号：US07734984B2

公开(公告)日：2010-06-08

申请号：US11595546

申请日：2006-11-10

Applicant: Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

Inventor： Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

IPC: H03M13/00

CPC classification number: H03M13/2936 ,  H03M13/2732 ,  H03M13/293

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract translation: 提供了一种擦除辅助块代码解码器及相关方法。 擦除辅助块码解码器包括第一块解码器，擦除处理器和第二块码解码器。 第一块解码器，例如Reed-Solomon解码器，被配置为对先前受突发错误影响的诸如字节的数据元素块进行解码。 第一块解码器还被配置为识别其不能解码的这些块的那些。 擦除处理器被配置为通过在擦除识别处理中利用由第一块解码器校正的解码块中的数据元素来识别不可解码块中的数据元素作为擦除。 第二块解码器，例如相同或不同的里德 - 所罗门解码器，被配置为通过在解码中利用由擦除处理器识别的擦除来解码一个或多个不可解码块。

公开(公告)号：US09042495B2

公开(公告)日：2015-05-26

申请号：US13560095

申请日：2012-07-27

Applicant: Fu-Hsuan Chiu ,  Chun-Hsuan Kuo

Inventor： Fu-Hsuan Chiu ,  Chun-Hsuan Kuo

IPC: H04B1/7107

CPC classification number: H04B1/71075 ,  H04B1/71055 ,  H04B1/71072

Abstract: In one embodiment, interference suppression is improved by improving convergence criteria. For some embodiments, convergence is improved by employing non-constant alpha-beta-weighting. For other embodiments, convergence is improved by employing successive interference suppression methods that have guaranteed convergence properties.

Abstract translation: 在一个实施例中，通过改进收敛标准来改善干扰抑制。 对于一些实施例，通过使用非常数α-β加权来提高收敛。 对于其他实施例，通过采用具有保证的收敛特性的连续的干扰抑制方法来提高收敛。

公开(公告)号：US20140029647A1

公开(公告)日：2014-01-30

申请号：US13560052

申请日：2012-07-27

Applicant: Fu-Hsuan Chiu ,  Bin Liu ,  Wei Luo ,  Chun-Hsuan Kuo

Inventor： Fu-Hsuan Chiu ,  Bin Liu ,  Wei Luo ,  Chun-Hsuan Kuo

IPC: H04B1/7103 ,  H04L27/01

CPC classification number: H04B1/7103 ,  H04B1/7107 ,  H04B1/711 ,  H04B2201/70702 ,  H04J11/004 ,  H04J11/005 ,  H04J11/0063

Abstract: In one embodiment, intra-cell interference suppression is achieved upstream of a chip-level equalizer, thereby mitigating downstream processing resources.

Abstract translation: 在一个实施例中，在芯片级均衡器的上游实现小区内干扰抑制，从而减轻下游处理资源。

公开(公告)号：US20130259093A1

公开(公告)日：2013-10-03

申请号：US13564282

申请日：2012-08-01

Applicant: Chun-Hsuan Kuo

Inventor： Chun-Hsuan Kuo

IPC: H04L27/01 ,  H04B1/7085 ,  H04L7/02

CPC classification number: H01Q1/243 ,  G01C21/26 ,  H03H7/40 ,  H04L25/03038 ,  H04L27/2647

Abstract: Various embodiments are disclosed for providing timing tracking loops in a communication system. A communication system includes a delay locked loop (DLL) comprising a maximum region detector configured to identify a target channel profile comprising at least a portion of the multipath signals based on the timing information, the maximum region detector further configured to apply a weight vector to each channel tap in the target channel profile and determine a tap with a maximum power level relative to remaining channel taps in the channel profile. The system further comprises a window timing loop (WTL) adjuster configured to track a position of a channel estimation window (CEW) within an observation window corresponding to the maximum channel energy level, where the maximum channel energy level corresponds to the sum of the energy of all the taps for a given window.

Abstract translation: 公开了用于在通信系统中提供定时跟踪环的各种实施例。 通信系统包括延迟锁定环路（DLL），该延迟锁定环路（DLL）包括最大区域检测器，该最大区域检测器被配置为基于该定时信息来识别包括至少一部分多路径信号的目标信道简档，该最大区域检测器还被配置为将权重向量应用于 每个通道在目标通道配置文件中点击，并确定相对于通道配置文件中剩余通道抽头的最大功率级别的抽头。 该系统还包括窗口定时循环（WTL）调整器，其被配置为跟踪对应于最大信道能级的观测窗内的信道估计窗口（CEW）的位置，其中最大信道能级对应于能量之和 在给定的窗口的所有水龙头。

公开(公告)号：US20100229070A1

公开(公告)日：2010-09-09

申请号：US12781749

申请日：2010-05-17

Applicant: Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

Inventor： Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

IPC: H03M13/29 ,  H03M13/07 ,  G06F11/10

CPC classification number: H03M13/2936 ,  H03M13/2732 ,  H03M13/293

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract translation: 提供了一种擦除辅助块代码解码器及相关方法。 擦除辅助块码解码器包括第一块解码器，擦除处理器和第二块码解码器。 第一块解码器，例如Reed-Solomon解码器，被配置为对先前受突发错误影响的诸如字节的数据元素块进行解码。 第一块解码器还被配置为识别其不能解码的这些块的那些。 擦除处理器被配置为通过在擦除识别处理中利用由第一块解码器校正的解码块中的数据元素来识别不可解码块中的数据元素作为擦除。 第二块解码器，例如相同或不同的里德 - 所罗门解码器，被配置为通过在解码中利用由擦除处理器识别的擦除来解码一个或多个不可解码块。

公开(公告)号：US09484620B2

公开(公告)日：2016-11-01

申请号：US13564282

申请日：2012-08-01

Applicant: Chun-Hsuan Kuo

Inventor： Chun-Hsuan Kuo

IPC: H04B1/00 ,  H04B7/216 ,  H01Q1/24 ,  G01C21/26 ,  H03H7/40

CPC classification number: H01Q1/243 ,  G01C21/26 ,  H03H7/40 ,  H04L25/03038 ,  H04L27/2647

Abstract: Various embodiments are disclosed for providing timing tracking loops in a communication system. A communication system includes a delay locked loop (DLL) comprising a maximum region detector configured to identify a target channel profile comprising at least a portion of the multipath signals based on the timing information, the maximum region detector further configured to apply a weight vector to each channel tap in the target channel profile and determine a tap with a maximum power level relative to remaining channel taps in the channel profile. The system further comprises a window timing loop (WTL) adjuster configured to track a position of a channel estimation window (CEW) within an observation window corresponding to the maximum channel energy level, where the maximum channel energy level corresponds to the sum of the energy of all the taps for a given window.

Abstract translation: 公开了用于在通信系统中提供定时跟踪环的各种实施例。 通信系统包括延迟锁定环路（DLL），该延迟锁定环路（DLL）包括最大区域检测器，该最大区域检测器被配置为基于该定时信息来识别包括至少一部分多路径信号的目标信道简档，该最大区域检测器还被配置为将权重向量应用于 每个通道在目标通道配置文件中点击，并确定相对于通道配置文件中剩余通道抽头的最大功率级别的抽头。 该系统还包括窗口定时循环（WTL）调整器，其被配置为跟踪对应于最大信道能级的观测窗内的信道估计窗口（CEW）的位置，其中最大信道能级对应于能量之和 在给定的窗口的所有水龙头。

公开(公告)号：US20070245208A1

公开(公告)日：2007-10-18

申请号：US11595546

申请日：2006-11-10

Applicant: Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

Inventor： Chi-Ping Nee ,  Abraham Krieger ,  Shachar Kons ,  Chun-Hsuan Kuo

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/2936 ,  H03M13/2732 ,  H03M13/293

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract translation: 提供了一种擦除辅助块代码解码器及相关方法。 擦除辅助块码解码器包括第一块解码器，擦除处理器和第二块码解码器。 第一块解码器，例如Reed-Solomon解码器，被配置为对先前受突发错误影响的诸如字节的数据元素块进行解码。 第一块解码器还被配置为识别其不能解码的这些块的那些。 擦除处理器被配置为通过在擦除识别处理中利用由第一块解码器校正的解码块中的数据元素来识别不可解码块中的数据元素作为擦除。 第二块解码器，例如相同或不同的里德 - 所罗门解码器，被配置为通过在解码中利用由擦除处理器识别的擦除来解码一个或多个不可解码块。

公开(公告)号：US08743930B2

公开(公告)日：2014-06-03

申请号：US13560052

申请日：2012-07-27

Applicant: Fu-Hsuan Chiu ,  Bin Liu ,  Wei Luo ,  Chun-Hsuan Kuo

Inventor： Fu-Hsuan Chiu ,  Bin Liu ,  Wei Luo ,  Chun-Hsuan Kuo

IPC: H04B1/00

CPC classification number: H04B1/7103 ,  H04B1/7107 ,  H04B1/711 ,  H04B2201/70702 ,  H04J11/004 ,  H04J11/005 ,  H04J11/0063

Abstract: Various embodiments are directed towards suppressing inter-cell and intra-cell interference. In some embodiments, an intra-cell interference signal for a specified rake finger is received. An inter-cell interference signal is received. The intra-cell interference signals upstream of a chip-level equalizer are suppressed. The inter-cell interference signals upstream of the chip-level equalizer are suppressed.

Abstract translation: 各种实施例涉及抑制细胞间和细胞内干扰。 在一些实施例中，接收用于指定的耙指的小区内干扰信号。 接收小区间干扰信号。 抑制芯片级均衡器上游的小区内干扰信号。 抑制芯片级均衡器上游的小区间干扰信号。