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    Process for preparing titanyl phthalocyanine
    3.
    发明申请
    Process for preparing titanyl phthalocyanine 审中-公开
    制备氧钛酞菁的方法

    公开(公告)号：US20070155962A1

    公开(公告)日：2007-07-05

    申请号：US11322077

    申请日：2005-12-30

    申请人： Ling Lu ,  Chang-Yu Chou ,  Chang-Li Cheng ,  Po-Han Huang ,  Yuan-Szu Chang ,  Nien-Szu Huang ,  Shyue-Ming Jang

    发明人： Ling Lu ,  Chang-Yu Chou ,  Chang-Li Cheng ,  Po-Han Huang ,  Yuan-Szu Chang ,  Nien-Szu Huang ,  Shyue-Ming Jang

    IPC分类号： C07D487/22

    CPC分类号： C07D487/22

    摘要： A process for preparing titanyl phthalocyanines in one reaction reactor includes the reaction of titanium tetrachloride or titanium trichloride and o-phthalodinitrile in an organic solvent such as 1-chloronaphthalene in the presence of a molecular sieve as a promoter followed by hydrolysis resulting in titanyl phthalocyanines. The prepared titanyl phthalocyanines is usable as a high-quality charge generating material and can be used as a charge generating layer in an organic photoconductor drum.

    摘要翻译： 在一个反应​​反应器中制备氧钛酞菁的方法包括在分子筛作为助催化剂存在下，在有机溶剂如1-氯萘中的四氯化钛或三氯化钛与邻二甲苯二腈反应，然后水解，得到氧钛酞菁。 制备的钛酞菁可用作高质量电荷产生材料，并可用作有机感光鼓中的电荷产生层。

    Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer
    4.
    发明授权
    Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer 有权
    动态可重构级流水线数据通路与数据有效信号控制多路复用器

    公开(公告)号：US07406588B2

    公开(公告)日：2008-07-29

    申请号：US11229616

    申请日：2005-09-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3869

    摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

    摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

    DIGITAL SIGNAL PROCESSOR
    5.
    发明申请
    DIGITAL SIGNAL PROCESSOR 有权
    数字信号处理器

    公开(公告)号：US20080172546A1

    公开(公告)日：2008-07-17

    申请号：US11679028

    申请日：2007-02-26

    申请人： Chuan-Cheng Peng ,  Po-Han Huang

    发明人： Chuan-Cheng Peng ,  Po-Han Huang

    IPC分类号： G06F15/76

    CPC分类号： G06F9/3012 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/342 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3885 ,  G06F9/3891

    摘要： A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping-pong register providing exclusively accessible data storage, and a public register file. The public register file comprises at least two read ports, each coupled to a function unit, providing read accessibility for the function units, and one write port to write data to the public register file.

    摘要翻译： 提供了一种数字信号处理器，包括至少一个群集。 集群可以包括至少两个功能单元，每个功能单元执行不同的指令类型，每个与用于数据存储的一个功能单元相关联的至少两个专用寄存器文件，提供专用可访问数据存储器的乒乓寄存器和公共寄存器文件。 公共登记文件包括至少两个读端口，每个读端口耦合到功能单元，提供功能单元的读取可访问性，以及一个写入端口将数据写入公共寄存器文件。

    Pipelined datapath with dynamically reconfigurable pipeline stages
    7.
    发明申请
    Pipelined datapath with dynamically reconfigurable pipeline stages 有权
    具有动态可重构流水线阶段的流水线数据路径

    公开(公告)号：US20060259748A1

    公开(公告)日：2006-11-16

    申请号：US11229616

    申请日：2005-09-20

    申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3869

    摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

    摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

    Inter-cluster communication module using the memory access network
    8.
    发明申请
    Inter-cluster communication module using the memory access network 有权
    群集间通信模块使用内存接入网

    公开(公告)号：US20060212663A1

    公开(公告)日：2006-09-21

    申请号：US11246115

    申请日：2005-10-11

    申请人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    发明人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

    IPC分类号： G06F12/00

    CPC分类号： G06F15/173

    摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

    摘要翻译： 提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。 当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项 通过交换设备向发布加载指令的集群发出存储指令，由此实现集群之间的数据交换。 这里，数据项根据地址被选择性地存储在存储器模块中。 此外，数据项也通过交换设备在存储器和簇之间传输。

    Apparatus For Cooperative Sharing Of Operand Access Port Of A Banked Register File
    9.
    发明申请
    Apparatus For Cooperative Sharing Of Operand Access Port Of A Banked Register File 审中-公开
    用于共享存储文件的操作数接入端口的装置

    公开(公告)号：US20070239970A1

    公开(公告)日：2007-10-11

    申请号：US11278824

    申请日：2006-04-06

    申请人： I-Tao Liao ,  Chuan-Cheng Peng ,  Po-Han Huang ,  Chuan-Hua Chang

    发明人： I-Tao Liao ,  Chuan-Cheng Peng ,  Po-Han Huang ,  Chuan-Hua Chang

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3012 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/3891

    摘要： An apparatus for cooperative sharing of operand access port of a banked register file comprises a partitioned register file, a first group of functional unit, a second group of function units and an access control circuit. The access control circuit includes three control bits to control the accesses to the register file by the functional units for operands. The invention is to relax the constraint encountered by the compiler and a smart assembler using a conventional Ping-Pong file register. The relaxed constraint allows the two banks of the partitioned register file accessed by two instructions simultaneously as long as each corresponding operand of the two instructions are in different register banks. By the relaxed constraint, a compiler and a smart assembler have more choices to schedule instructions in a program, potentially increasing program performance.

    摘要翻译： 一种用于协同共享存储寄存器文件的操作数访问端口的装置，包括分区寄存器文件，第一组功能单元，第二组功能单元和访问控制电路。 访问控制电路包括三个控制位，用于控制功能单元对操作数对寄存器文件的访问。 本发明是为了放松使用传统乒乓文件寄存器的编译器和智能汇编器遇到的约束。 宽松的约束允许两个指令同时访问的分区寄存器文件的两个库，只要两个指令的每个相应的操作数都在不同的寄存器组中。 通过轻松的约束，编译器和智能汇编器有更多的选择来调度程序中的指令，从而潜在地增加程序性能。