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1.发明授权公开(公告)号：US07159198B1
公开(公告)日：2007-01-02
申请号：US10745993
申请日：2003-12-24
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention is directed to a system and a method for verifying properties of a circuit model while providing information to help the user manually modify a design analysis region and/or environmental constraints. While conventional systems attempt to substantially automate the entire formal verification process, the present invention iteratively provides information to the user about the cost and effect of changes to the environmental constraints and the analysis region. This information enables the user to weigh the effectiveness and efficiency of one or more modifications to the design analysis area and/or to the environmental constraints (assumptions). The information provided to the user can help a user compare a variety of alternative modifications in order to select the modifications that are efficient and effective. In addition, the information can provide alternatives along with the cost and effect of each alternative to the user who otherwise did not identify these alternatives, thus the invention can help the user by identifying suggestions that the user may not have otherwise considered. The present invention then receives information from the user to modify the design analysis area and/or the environmental constraints and will analyze the design with these modified parameters.
摘要翻译： 本发明涉及一种用于验证电路模型的属性的系统和方法，同时提供信息以帮助用户手动修改设计分析区域和/或环境约束。 虽然常规系统试图使整个形式验证过程大幅自动化，但是本发明向用户反复地提供关于环境约束和分析区域的改变的成本和效果的信息。 该信息使用户能够对设计分析区域和/或环境约束（假设）的一个或多个修改的有效性和效率进行权衡。 提供给用户的信息可以帮助用户比较各种替代修改以选择有效和有效的修改。 此外，该信息可以提供替代方案以及用户的每个备选方案的成本和效果，否则其中没有识别这些替代方案，因此本发明可以通过识别用户可能没有另外考虑的建议来帮助用户。 然后，本发明从用户接收信息以修改设计分析区域和/或环境约束，并将用这些修改的参数分析设计。
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2.发明授权Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction 有权提取，可视化和对电路设计与其抽象之间的不一致行为公开(公告)号：US07895552B1
公开(公告)日：2011-02-22
申请号：US11092994
申请日：2005-03-28
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In the field of functional verification of digital designs in systems that use an abstraction for portions of a circuit design to perform the verification proof, a tool is described for resolving inconsistencies between the design and abstractions for the design. The tool provides information to a user about intermediate steps in the verification process. In response, the user may provide insight about the design to allow the tool to adjust the verification analysis of the design. The information provided to the user, including possible conflicts between the design and its abstractions, may include visualization techniques to facilitate the user's understating of any inconsistencies.
摘要翻译： 在使用电路设计部分的抽象来执行验证证明的系统中的数字设计的功能验证领域中，描述了用于解决设计和设计抽象之间不一致的工具。 该工具向用户提供有关验证过程中的中间步骤的信息。 作为响应，用户可以提供关于设计的洞察，以允许工具调整设计的验证分析。 提供给用户的信息，包括设计与其抽象之间可能的冲突，可能包括可视化技术，以便于用户低估任何不一致之处。
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3.发明授权Managing formal verification complexity of designs with multiple related counters 有权用多个相关计数器管理设计的正式验证复杂性公开(公告)号：US07647572B1
公开(公告)日：2010-01-12
申请号：US11851330
申请日：2007-09-06
CPC分类号： G06F17/504 , G06F17/5022
摘要： A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.
摘要翻译： 计数器抽象工具为电路设计中的一个或多个计数器生成抽象模型，以便与形式验证系统一起使用。 该工具检测电路设计中存在计数器，识别计数器的一个或多个特殊值，并为计数器创建抽象。 该工具可以自动执行抽象，指导用户配置计数器的适当抽象，或执行自动和手动抽象的组合。 该工具可以进一步容纳相关的计数器。
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4.发明授权System and method for guiding and optimizing formal verification for a circuit design 失效指导和优化电路设计形式验证的系统和方法公开(公告)号：US07065726B1
公开(公告)日：2006-06-20
申请号：US10606419
申请日：2003-06-26
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.
摘要翻译： 本发明用于指导电路仿真软件中电路设计的形式验证，以优化电路设计验证所需的时间。 本发明修改了用于验证的分析区域，以优化验证时间。 本发明允许分析区域的手动，半自动和自动修改。 修改是通过扩展或减少分析区域或通过添加新规则作为现有分析区域的假设来完成的。 本发明还使用用于修改分析区域的关节点的概念。 分析区域的修改以优化验证电路设计所需的时间和存储器的方式来执行。
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公开(公告)号：US07418678B1
公开(公告)日：2008-08-26
申请号：US10909099
申请日：2004-07-29
申请人： Chung-Wah N Ip , Lawrence Loh , Vigyan Singhal , Howard Wong-Toi
发明人： Chung-Wah N Ip , Lawrence Loh , Vigyan Singhal , Howard Wong-Toi
CPC分类号： G06F17/504 , G06F17/5022
摘要： A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.
摘要翻译： 计数器抽象工具为电路设计中的一个或多个计数器生成抽象模型，以便与形式验证系统一起使用。 该工具检测电路设计中存在计数器，识别计数器的一个或多个特殊值，并为计数器创建抽象。 该工具可以自动执行抽象，指导用户配置计数器的适当抽象，或执行自动和手动抽象的组合。 该工具可以进一步容纳相关的计数器。
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6.发明申请公开(公告)号：US20090119631A1
公开(公告)日：2009-05-07
申请号：US12265657
申请日：2008-11-05
申请人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer
发明人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer
IPC分类号： G06F17/50
CPC分类号： H03L7/00 , G06F17/505 , G06F2217/14 , H03K19/20
摘要： A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
摘要翻译： 用于将给定的同步电路描述自动变换为等效且可证明的正确的非同步电路描述的系统。 包括在自动变换中的技术是使用两相协议合成可变性感知控制器的技术，使用门控时钟和可测试性电路合成可变性感知控制器的技术，用于合成针对性能优化的可变性感知控制器的技术 初始化合成控制器，用于动态最小化功率需求的技术，以及将失步电路与外部同步电路接口的技术。 还公开了用于实现用于在电子设计自动化设计流程的上下文中将同步电路描述自动变换为等同且可证明的正确的不同步电路描述的系统的技术。 提供了在上述技术的应用中使用的示例性电路。 介绍并解释了用于证明输入描述和所得到的非同步电路之间等价性的数学模型和技术的应用。
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7.发明申请Variability-Aware Asynchronous Scheme for High-Performance Communication Between an Asynchronous Circuit and a Synchronous Circuit 审中-公开用于异步电路和同步电路之间高性能通信的可变性感知异步方案公开(公告)号：US20090116597A1
公开(公告)日：2009-05-07
申请号：US12265620
申请日：2008-11-05
申请人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer , Luciano Lavagno
发明人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer , Luciano Lavagno
CPC分类号： H03L7/00 , G06F17/505 , G06F2217/14 , H03K19/20
摘要： A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
摘要翻译： 用于将给定的同步电路描述自动变换为等效且可证明的正确的非同步电路描述的系统。 包括在自动变换中的技术是使用两相协议合成可变性感知控制器的技术，使用门控时钟和可测试性电路合成可变性感知控制器的技术，用于合成针对性能优化的可变性感知控制器的技术 初始化合成控制器，用于动态最小化功率需求的技术，以及将失步电路与外部同步电路接口的技术。 还公开了用于实现用于在电子设计自动化设计流程的上下文中将同步电路描述自动变换为等同且可证明的正确的不同步电路描述的系统的技术。 提供了在上述技术的应用中使用的示例性电路。 介绍并解释了用于证明输入描述和所得到的非同步电路之间等价性的数学模型和技术的应用。
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公开(公告)号：US20090115469A1
公开(公告)日：2009-05-07
申请号：US12265571
申请日：2008-11-05
申请人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer
发明人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F17/505 , G06F2217/14 , H03K19/20
摘要： A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
摘要翻译： 用于将给定的同步电路描述自动变换为等效且可证明的正确的非同步电路描述的系统。 包括在自动变换中的技术是使用两相协议合成可变性感知控制器的技术，使用门控时钟和可测试性电路合成可变性感知控制器的技术，用于合成针对性能优化的可变性感知控制器的技术 初始化合成控制器，用于动态最小化功率需求的技术，以及将失步电路与外部同步电路接口的技术。 还公开了用于实现用于在电子设计自动化设计流程的上下文中将同步电路描述自动变换为等同且可证明的正确的不同步电路描述的系统的技术。 提供了在上述技术的应用中使用的示例性电路。 介绍并解释了用于证明输入描述和所得到的非同步电路之间等价性的数学模型和技术的应用。
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9.发明授权System and method for measuring progress for formal verification of a design using analysis region 有权使用分析区域对设计进行正式验证的进度的系统和方法公开(公告)号：US07412674B1
公开(公告)日：2008-08-12
申请号：US11089851
申请日：2005-03-24
申请人： Vigyan Singhal , Brajesh Arora , Yann Antonioli
发明人： Vigyan Singhal , Brajesh Arora , Yann Antonioli
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and apparatus for measuring the progress of a formal verification process using an analysis region, and measures the effectiveness of the current set of properties/requirements in verifying different portions of logic within the design. The present invention applies the concept of analysis region to analyze the properties/requirements for a design. The analysis region can be expanded or contracted either manually or automatically based upon the results of the analysis. The present invention generates a visual display that is available to the user that represents the amount of source code in the analysis region for a given property or multiple properties in comparison to the maximum possible analysis region. The present invention can display this information in a bar graph format, on a line-by-line basis for the source code and on a waveform display, for example.
摘要翻译： 一种用于测量使用分析区域的形式验证过程的进度的方法和装置，并且测量在验证设计中的逻辑的不同部分的当前属性/要求集合的有效性。 本发明应用分析区域的概念来分析设计的性质/要求。 分析区域可以根据分析结果手动或自动扩展或收缩。 与最大可能分析区域相比，本发明生成可用于表示给定属性或多个属性的分析区域中的源代码量的用户的视觉显示。 例如，本发明可以以条形图格式，逐行显示源代码和波形显示。
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10.发明申请Variability-Aware Scheme for High-Performance Asynchronous Circuit Voltage Reglulation 有权用于高性能异步电路电压调节的可变性意识方案公开(公告)号：US20090115503A1
公开(公告)日：2009-05-07
申请号：US12265585
申请日：2008-11-05
申请人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer , Luciano Lavagno
发明人： Jordi Cortadella , Vigyan Singhal , Emre Tuncer , Luciano Lavagno
IPC分类号： G05F1/10
CPC分类号： H03L7/00 , G06F17/505 , G06F2217/14 , H03K19/20
摘要： A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
摘要翻译： 用于将给定的同步电路描述自动变换为等效且可证明的正确的非同步电路描述的系统。 包括在自动变换中的技术是使用两相协议合成可变性感知控制器的技术，使用门控时钟和可测试性电路合成可变性感知控制器的技术，用于合成针对性能优化的可变性感知控制器的技术 初始化合成控制器，用于动态最小化功率需求的技术，以及将失步电路与外部同步电路接口的技术。 还公开了用于实现用于在电子设计自动化设计流程的上下文中将同步电路描述自动变换为等同且可证明的正确的不同步电路描述的系统的技术。 提供了在上述技术的应用中使用的示例性电路。 介绍并解释了用于证明输入描述和所得到的非同步电路之间等价性的数学模型和技术的应用。
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