Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal
    1.
    发明申请
    Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal 有权
    双级源极/漏极延伸结退火以减少结深度:多脉冲低能激光退火与快速热退火相结合

    公开(公告)号:US20050158956A1

    公开(公告)日:2005-07-21

    申请号:US10759671

    申请日:2004-01-16

    摘要: A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.

    摘要翻译: 描述了一种工艺以在源极/漏极延伸区域中形成具有浅结的诸如MOSFET或CMOS的半导体器件。 在形成浅沟槽隔离物和栅极堆叠之后,去除侧壁电介质间隔物。 用Ge + +或Si + +离子进行预非晶化植入物(PAI),以在邻近栅叠层的硅区域的表面上形成薄的PAI层。 然后进行离子注入以形成源极/漏极延伸(SDE)区域。 然后,B + / /> /注入步骤之后是脉冲持续时间为23ns的多脉冲248nm KrF准分子激光退火。 该步骤是通过SDE结中的硼掺杂剂的激活来降低结的薄层电阻。 然后激光退火之后是快速热退火(RTA),以修复残余损伤,并且还引起硼的扩散,从而产生比RTA之前刚刚植入的结更浅的结。