公开(公告)号：US20180357124A1

公开(公告)日：2018-12-13

申请号：US15984108

申请日：2018-05-18

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Rahul GAWDE ,  Michael A. KOST ,  Alvin C. STORVIK

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1575 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/2942 ,  H03M13/2948

Abstract: An error correction code for an array of N words of M bits each may be generated by: (i) for each word of the N words, computing a respective set of checkbits for single-error correction of such word; (ii) computing a set of bit-position-related checkbits comprising a bitwise logical exclusive OR of all of the sets of checkbits for single-error correction of the N words; (iii) for each word of the N words, computing a respective parity for the respective set of checkbits and the word itself in order to form a vector of N parity bits; (iv) computing a set of word-related checkbits for single-error correction of the vector of N parity bits; and (v) computing a cumulative parity bit comprising a parity calculation of the set of bit-position-related checkbits, the set of word-related checkbits, and the vector of N parity bits.