公开(公告)号：US12169720B2

公开(公告)日：2024-12-17

申请号：US17957708

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/4401 ,  G06F8/65 ,  G06F9/38

Abstract: A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

公开(公告)号：US20230083300A1

公开(公告)日：2023-03-16

申请号：US17957614

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/38 ,  G06F9/4401

Abstract: A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.

公开(公告)号：US12164925B2

公开(公告)日：2024-12-10

申请号：US17957614

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/38 ,  G06F9/4401

Abstract: A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.

公开(公告)号：US20230080059A1

公开(公告)日：2023-03-16

申请号：US17957708

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/4401 ,  G06F9/38 ,  G06F8/65

Abstract: A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.