公开(公告)号：US12034442B2

公开(公告)日：2024-07-09

申请号：US17948442

申请日：2022-09-20

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Donelson A. Shannon ,  Jianping Wen

IPC: G11C5/14 ,  G11C17/00 ,  H03K19/0185

CPC classification number: H03K19/018507 ,  G11C5/14 ,  G11C17/00

Abstract: A system may include a first power domain defined by a first supply rail and a first ground rail, a second power domain defined by a second supply rail and a second ground rail, and a configurable switch coupled between the first ground rail and the second ground rail such that when the configurable switch is enabled, the first ground rail and the second ground rail are electrically shorted to one another and when the configurable switch is disabled, the first ground rail and the second ground rail are electrically isolated from one another.

公开(公告)号：US11888492B2

公开(公告)日：2024-01-30

申请号：US17683650

申请日：2022-03-01

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Inventor： Jianping Wen ,  John L. Melanson

IPC: H03M1/06

CPC classification number: H03M1/0607

Abstract: A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.

公开(公告)号：US20230283286A1

公开(公告)日：2023-09-07

申请号：US17683650

申请日：2022-03-01

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Inventor： Jianping Wen ,  John L. Melanson

IPC: H03M1/06

CPC classification number: H03M1/0607

Abstract: A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.

公开(公告)号：US10951225B1

公开(公告)日：2021-03-16

申请号：US16821667

申请日：2020-03-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Donelson A. Shannon ,  Edmund M. Schneider ,  Jianping Wen

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/12

Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC including a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

公开(公告)号：US12160248B2

公开(公告)日：2024-12-03

申请号：US18098544

申请日：2023-01-18

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vamsikrishna Parupalli ,  Mikel Ash ,  Jianping Wen ,  Melvin L. Hagge

IPC: H03M1/46 ,  H03M1/80

Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.