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公开(公告)号：US11502671B2
公开(公告)日：2022-11-15
申请号：US17162950
申请日：2021-01-29
Inventor： Qiang Li , Rahul Singh , Paul Astrachan , Kyehyung Lee
Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.
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公开(公告)号：US10812074B2
公开(公告)日：2020-10-20
申请号：US16582528
申请日：2019-09-25
Inventor： Yongjie Cheng , Lei Zhu , Kyehyung Lee
Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.
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3.发明授权公开(公告)号：US11296685B2
公开(公告)日：2022-04-05
申请号：US16996779
申请日：2020-08-18
Inventor： Ramin Zanbaghi , Anuradha Parsi , Kyehyung Lee , John L. Melanson
Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.
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4.发明申请公开(公告)号：US20210044285A1
公开(公告)日：2021-02-11
申请号：US16996779
申请日：2020-08-18
Inventor： Ramin Zanbaghi , Anuradha Parsi , Kyehyung Lee , John L. Melanson
Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.
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Patent Agency Ranking
公开(公告)号：US10819328B2
公开(公告)日：2020-10-27
申请号：US16163766
申请日：2018-10-18
Inventor： Ramin Zanbaghi , Anuradha Parsi , Kyehyung Lee , John L. Melanson
Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.
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公开(公告)号：US10476502B2
公开(公告)日：2019-11-12
申请号：US15582257
申请日：2017-04-28
Inventor： Yongjie Cheng , Lei Zhu , Kyehyung Lee
IPC: H03K19/00 , H03K17/06 , H03K19/04 , H03F1/02 , H03G1/00 , H03K19/094 , H03F3/187 , H03F3/217 , H03F3/45
Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.
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公开(公告)号：US20220247389A1
公开(公告)日：2022-08-04
申请号：US17162950
申请日：2021-01-29
Inventor： Qiang Li , Rahul Singh , Paul Astrachan , Kyehyung Lee
Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.
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公开(公告)号：US10659029B2
公开(公告)日：2020-05-19
申请号：US16163638
申请日：2018-10-18
Inventor： Ramin Zanbaghi , Anuradha Parsi , Kyehyung Lee , John L. Melanson
Abstract: An apparatus in a PWM modulator includes a triangular wave generator that generates a triangular wave and a comparator that is responsive to a signal input to generate a signal output. An output of the PWM modulator is responsive to the comparator signal output. A polarity inversion circuit, coupled between the triangular wave generator and the comparator, is configured in one of the following ways: to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity.
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公开(公告)号：US10476455B1
公开(公告)日：2019-11-12
申请号：US16057820
申请日：2018-08-08
Inventor： Paul Astrachan , Emmanuel Marchais , Lingli Zhang , Zhaohui He , Kyehyung Lee , Tejasvi Das , John L. Melanson
Abstract: A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.
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