SUBMOUNT FOR SEMICONDUCTOR LASER AND OPTICAL FIBERS

    公开(公告)号:US20200044412A1

    公开(公告)日:2020-02-06

    申请号:US16052441

    申请日:2018-08-01

    Abstract: A submount assembly comprises a first substrate having a first surface and an opposing second surface, wherein a plurality of first grooves are formed into the first substrate from the first surface. Each first groove is dimensioned to receive a portion of a respective optical fiber of a plurality of optical fibers, and to arrange the optical fiber with a predetermined first height relative to the first surface. The submount assembly further comprises a plurality of first conductive traces on a side of the first substrate corresponding to the first surface, and a semiconductor laser contacted with the first conductive traces. The semiconductor laser has a predetermined second height relative to the first surface. The submount assembly further comprises a plurality of second conductive traces at the second surface and a plurality of first vias extending through the first substrate from the first conductive traces to the second conductive traces.

    PASSIVE FIBER TO CHIP COUPLING USING POST-ASSEMBLY LASER PATTERNED WAVEGUIDES

    公开(公告)号:US20200241207A1

    公开(公告)日:2020-07-30

    申请号:US16260622

    申请日:2019-01-29

    Abstract: Using laser patterning for an optical assembly, optical features are written into photonic elements at the end of a manufacturing sequence in order to prevent errors and damages to the optical features. The optical assembly is manufactured by affixing a photonic element to a substrate which includes one or more optical features and mapping one or more optical features for the photonic element. The optical features are then written into the fixed photonic element using laser patterning and the optical assembly is completed by connecting components, such as optical fibers, to the photonic element.

    FIBER COUPLER WITH AN OPTICAL WINDOW
    3.
    发明申请

    公开(公告)号:US20190310431A1

    公开(公告)日:2019-10-10

    申请号:US15946930

    申请日:2018-04-06

    Abstract: Embodiments herein describe a fiber array unit (FAU) configured to optically couple a photonic chip with a plurality of optical fibers. Epoxy can be used to bond the FAU to the photonic chip. However, curing the epoxy between the FAU and the photonic chip is difficult. As such, the FAU can include one or more optical windows etched into or completely through a non-transparent layer that overlap the epoxy disposed on the photonic chip. UV radiation can be emitted through the optical windows to cure the underlying epoxy. In one example, the windows can also be used for dispensing epoxy. In addition to the optical windows, the FAU can include alignment protrusions (e.g., frustums) which mate or interlock with respective alignment receivers in the photonic chip. Doing so may facilitate passive alignment of the optical fibers in the FAU to an optical interface in the photonic chip.

    FIBER COUPLER WITH AN OPTICAL WINDOW

    公开(公告)号:US20210223487A1

    公开(公告)日:2021-07-22

    申请号:US17301407

    申请日:2021-04-01

    Abstract: A fiber array unit (FAU) includes a substrate, a plurality of optical fibers, and a lid. The substrate includes: an optical window extending through a layer of non-transparent material, a plurality of grooves, and an alignment protrusion configured to mate with an alignment receiver. The plurality of optical fibers are disposed in the plurality of grooves. The alignment protrusion is configured to align the plurality of optical fibers with an external device when mated with the alignment receiver. The plurality of optical fibers is disposed between the lid and the substrate.

    LASER PATTERNED ADAPTERS WITH WAVEGUIDES AND ETCHED CONNECTORS FOR LOW COST ALIGNMENT OF OPTICS TO CHIPS

    公开(公告)号:US20200049890A1

    公开(公告)日:2020-02-13

    申请号:US16058608

    申请日:2018-08-08

    Abstract: By determining an alignment point for a photonic element in a substrate of a given material; applying, via a laser aligned with the photonic element according to the alignment point, an etching pattern to the photonic element to produce a patterned region and an un-patterned region in the photonic element, wherein applying the etching pattern alters a chemical bond in the given material for the patterned region of the photonic element that increases a reactivity of the given material to an etchant relative to a reactivity of the un-patterned region, and wherein the patterned region defines an engagement feature in the un-patterned region that is configured to engage with a mating feature on a Photonic Integrated Circuit (PIC); and removing the patterned region from the photonic element via the etchant, various systems and methods may make use of laser patterning in optical components to enable alignment of optics to chips.

    FIBER TO CHIP ALIGNMENT USING PASSIVE VGROOVE STRUCTURES

    公开(公告)号:US20190285813A1

    公开(公告)日:2019-09-19

    申请号:US16146311

    申请日:2018-09-28

    Abstract: An apparatus comprises a plurality of optical fibers and a lid member having one or more surfaces with grooves formed therein. The lid member defines a first plurality of grooves that are each dimensioned to partly receive an optical fiber of the plurality of optical fibers. The apparatus further comprises a substrate comprising a plurality of waveguides arranged at a predefined depth relative to a reference surface of the substrate, and a plurality of ribs extending from the reference surface. Each rib of the plurality of ribs is dimensioned to engage with a respective groove of a second plurality of grooves of the lid member. Engaging the plurality of ribs of the substrate with the second plurality of grooves of the lid member provides an optical alignment of the plurality of optical fibers with the plurality of waveguides.

    INTEGRATED CIRCUIT BRIDGE FOR PHOTONICS AND ELECTRICAL CHIP INTEGRATION

    公开(公告)号:US20210280568A1

    公开(公告)日:2021-09-09

    申请号:US17302853

    申请日:2021-05-13

    Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.

    PERISCOPE OPTICAL ASSEMBLY
    9.
    发明申请

    公开(公告)号:US20210072461A1

    公开(公告)日:2021-03-11

    申请号:US17103735

    申请日:2020-11-24

    Abstract: The present disclosure provides for periscope optical assemblies within interposers that include a bulk material having a first side and a second side opposite to the first side; a first optic defined in the bulk material at a first height in the bulk material along an axis extending between the first second sides; a second optic defined in the bulk material at a second height in the bulk material, different than the first height, along the axis; a first waveguide defined in the bulk material, extending from the first side to the first optic; a second waveguide defined in the bulk material, extending from the second optic to the second side; and a third waveguide defined in the bulk material, extending from the first optic to the second optic.

    INTEGRATED CIRCUIT BRIDGE FOR PHOTONICS AND ELECTRICAL CHIP INTEGRATION

    公开(公告)号:US20190326266A1

    公开(公告)日:2019-10-24

    申请号:US15961163

    申请日:2018-04-24

    Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.

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