公开(公告)号：US20230060862A1

公开(公告)日：2023-03-02

申请号：US17445914

申请日：2021-08-25

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. PATEL ,  Matthew J. TRAVERSO ,  Sandeep RAZDAN ,  Aparna R. PRASAD

IPC: G02B6/42

Abstract: Embodiments herein describe an optical system that includes a photonic integrated circuit (PIC) bonded to a package containing an electrical integrated circuit (EIC). However, this bond can prevent an edge coupler from optically aligning an optical fiber to an edge of the PIC in order to transfer optical signals. To provide room for the edge coupler, the PIC is arranged to overhang the package containing the EIC so that the package does not interfere with the ability of the edge coupler to align with the side or edge of the PIC. In this manner, an optical fiber can be optically aligned (e.g., butt coupled) to the edge of the PIC rather than having to use a grating coupler or some other less efficient optical coupling in order to transfer optical signals between the PIC and the optical fiber.

公开(公告)号：US20210088722A1

公开(公告)日：2021-03-25

申请号：US16579330

申请日：2019-09-23

Applicant: Cisco Technology, Inc.

Inventor： Sandeep RAZDAN ,  Vipulkumar K. PATEL ,  Aparna R. PRASAD

IPC: G02B6/12 ,  G02B6/13 ,  H01L23/00 ,  B23K35/26

Abstract: Photonic devices include a photonic assembly and a substrate coupled to the photonic assembly. The photonic assembly includes a photonic die and an optical device coupled to the photonic die with an adhesive to form an optical connection between the optical device and the photonic die. The photonic assembly is coupled to the photonic assembly by reflowing a plurality of solder connections at temperature that is less than a cure temperature of the adhesive.

公开(公告)号：US20210055489A1

公开(公告)日：2021-02-25

申请号：US16544699

申请日：2019-08-19

Applicant: Cisco Technology, Inc.

Inventor： Ashley J. MAKER ,  Joyce J. M. PETERNEL ,  Sandeep RAZDAN ,  Matthew J. TRAVERSO ,  Aparna R. PRASAD

IPC: G02B6/42

Abstract: An optical connection assembly joining optical components is described. The optical connection assembly is manufactured using a fan out wafer level packaging to produce dies/frames which include mechanical connection features. A fastener is joined to a connection component and affixed to the mechanical connection features, to provide structural support to the connection between the connected component and the die/frame structure.

公开(公告)号：US20220278022A1

公开(公告)日：2022-09-01

申请号：US17663072

申请日：2022-05-12

Applicant: Cisco Technology, Inc.

Inventor： Ashley J.M. ERICKSON ,  Matthew J. TRAVERSO ,  Sandeep RAZDAN ,  Joyce J. M. PETERNEL ,  Aparna R. PRASAD

IPC: H01L23/473 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

公开(公告)号：US20210305128A1

公开(公告)日：2021-09-30

申请号：US16836825

申请日：2020-03-31

Applicant: Cisco Technology, Inc.

Inventor： Ashley J.M. ERICKSON ,  Matthew J. TRAVERSO ,  Sandeep RAZDAN ,  Joyce J.M. PETERNEL ,  Aparna R. PRASAD

IPC: H01L23/473 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

公开(公告)号：US20200241207A1

公开(公告)日：2020-07-30

申请号：US16260622

申请日：2019-01-29

Applicant: Cisco Technology, Inc.

Inventor： Sandeep RAZDAN ,  Ashley J. MAKER ,  Jock T. BOVINGTON ,  Matthew J. TRAVERSO

IPC: G02B6/30

Abstract: Using laser patterning for an optical assembly, optical features are written into photonic elements at the end of a manufacturing sequence in order to prevent errors and damages to the optical features. The optical assembly is manufactured by affixing a photonic element to a substrate which includes one or more optical features and mapping one or more optical features for the photonic element. The optical features are then written into the fixed photonic element using laser patterning and the optical assembly is completed by connecting components, such as optical fibers, to the photonic element.

公开(公告)号：US20220320765A1

公开(公告)日：2022-10-06

申请号：US17645195

申请日：2021-12-20

Applicant: Cisco Technology, Inc.

Inventor： Matthew J. TRAVERSO ,  Sandeep RAZDAN ,  Joyce J. M. PETERNEL

IPC: H01R12/70 ,  G02B6/38

Abstract: An apparatus includes a substrate, a frame, and a socket. The frame defines a slot. The frame is coupled to the substrate such that the slot is aligned with an attachment location on the substrate. The socket receives a first device. The socket aligns with the attachment location on the substrate when the socket is inserted in the slot.

公开(公告)号：US20210141154A1

公开(公告)日：2021-05-13

申请号：US16677404

申请日：2019-11-07

Applicant: Cisco Technology, Inc.

Inventor： Sandeep RAZDAN ,  Vipulkumar K. PATEL ,  Mark A. WEBSTER ,  Matthew J. TRAVERSO

IPC: G02B6/122 ,  G02B6/30 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/762

Abstract: Aspects described herein include a method comprising bonding a photonic wafer with an electronic wafer to form a wafer assembly, removing a substrate of the wafer assembly to expose a surface of the photonic wafer or of the electronic wafer, forming electrical connections between metal layers of the photonic wafer and metal layers of the electronic wafer, and adding an interposer wafer to the wafer assembly by bonding the interposer wafer with the wafer assembly at the exposed surface. The interposer wafer comprises through-vias that are electrically coupled with the metal layers of one or both of the photonic wafer and the electronic wafer. The method further comprises dicing the wafer assembly to form a plurality of dies. A respective edge coupler of each die is optically exposed at an interface formed by the dicing.

公开(公告)号：US20200319416A1

公开(公告)日：2020-10-08

申请号：US16522531

申请日：2019-07-25

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. PATEL ,  Aparna R. PRASAD ,  Sandeep RAZDAN

IPC: G02B6/42

Abstract: The present disclosure provides a frame lid assembly, which may be used in assembling an optical platform to provide isolated thermal conduction paths for various elements thereof. The frame lid assembly includes a first frame lid, including: a foot, disposed in a first plane; a roof, disposed in a second plane parallel to the first plane, the roof defining a port as a first through-hole that is perpendicular to the second plane; a wall, disposed obliquely to the first plane, separating the roof from the foot, the wall defining a slot as a second through-hole that is parallel to the first plane; a second frame lid connected to the first frame lid and thermally isolated from the first frame lid, the second frame lid including: a cap, connected to the roof via a thermal insulator; and a plug, extending perpendicularly from the cap through the port.

公开(公告)号：US20250012988A1

公开(公告)日：2025-01-09

申请号：US18347452

申请日：2023-07-05

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. PATEL ,  Sandeep RAZDAN

IPC: G02B6/42

Abstract: The present disclosure relates to an opto-electrical circuit and a method of forming an opto-electrical circuit. According to an embodiment, a circuit includes a photonic integrated circuit, an intermetal dielectric, an oxide layer, and a first electronic integrated circuit. The intermetal dielectric is coupled to the photonic integrated circuit. The oxide layer is coupled to the intermetal dielectric such that the intermetal dielectric is positioned between the photonic integrated circuit and the oxide layer. The first electronic integrated circuit is positioned within the oxide layer and coupled to the intermetal dielectric. A through oxide via extends through the oxide layer to the intermetal dielectric.