公开(公告)号：US11639955B2

公开(公告)日：2023-05-02

申请号：US17445616

申请日：2021-08-23

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Prajwal M. Kasturi ,  Joseph V. Pampanin ,  Craig S. Appel

IPC: G01R31/28

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.

公开(公告)号：US11099229B2

公开(公告)日：2021-08-24

申请号：US16740296

申请日：2020-01-10

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Prajwal M. Kasturi ,  Joseph V. Pampanin ,  Craig S. Appel

IPC: G01R31/28

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.

公开(公告)号：US20210215754A1

公开(公告)日：2021-07-15

申请号：US16740296

申请日：2020-01-10

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Prajwal M. Kasturi ,  Joseph V. Pampanin ,  Craig S. Appel

IPC: G01R31/28

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.