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公开(公告)号:US12095421B2
公开(公告)日:2024-09-17
申请号:US17810792
申请日:2022-07-05
Applicant: Cisco Technology, Inc.
Inventor: Craig S. Appel , Peter C. Metz , Joseph V. Pampanin , Sanjay Sunder
CPC classification number: H03F1/0211 , H03F3/45179 , H03F3/45663 , H03K5/2481
Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
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公开(公告)号:US11639955B2
公开(公告)日:2023-05-02
申请号:US17445616
申请日:2021-08-23
Applicant: Cisco Technology, Inc.
Inventor: Sanjay Sunder , Prajwal M. Kasturi , Joseph V. Pampanin , Craig S. Appel
IPC: G01R31/28
Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
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公开(公告)号:US11411538B2
公开(公告)日:2022-08-09
申请号:US16417295
申请日:2019-05-20
Applicant: Cisco Technology, Inc.
Inventor: Craig S. Appel , Peter C. Metz , Joseph V. Pampanin , Sanjay Sunder
Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
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公开(公告)号:US11099229B2
公开(公告)日:2021-08-24
申请号:US16740296
申请日:2020-01-10
Applicant: Cisco Technology, Inc.
Inventor: Sanjay Sunder , Prajwal M. Kasturi , Joseph V. Pampanin , Craig S. Appel
IPC: G01R31/28
Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
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公开(公告)号:US20210215754A1
公开(公告)日:2021-07-15
申请号:US16740296
申请日:2020-01-10
Applicant: Cisco Technology, Inc.
Inventor: Sanjay Sunder , Prajwal M. Kasturi , Joseph V. Pampanin , Craig S. Appel
IPC: G01R31/28
Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
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