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    Method and apparatus for calibrating a delay locked loop charge pump current
    1.
    发明授权
    Method and apparatus for calibrating a delay locked loop charge pump current 有权
    用于校准延迟锁定环电荷泵电流的方法和装置

    公开(公告)号：US06788045B2

    公开(公告)日：2004-09-07

    申请号：US10147594

    申请日：2002-05-17

    申请人： Claude R. Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

    发明人： Claude R. Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

    IPC分类号： G01R2312

    CPC分类号： H03L7/0812 ,  H03L7/0896

    摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.

    摘要翻译： 提供了一种用于后期制造控制延迟锁定环电荷泵电流的校准和调整系统。 校准和调节系统包括改变电荷泵电流量的调节装置。 在延迟锁定环路中对电荷泵电流的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。 可以存储并随后读取电荷泵电流期望的调节量的代表值来调整延迟锁定环路。

    Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump
    2.
    发明授权
    Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump 有权
    锁相环电荷泵后处理调整校准系统

    公开(公告)号：US06768955B2

    公开(公告)日：2004-07-27

    申请号：US10147707

    申请日：2002-05-17

    申请人： Claude R. Gauthier ,  Brian W. Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude R. Gauthier ,  Brian W. Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： G01R2300

    CPC分类号： H03L7/0896 ,  H03L7/18

    摘要： An adjustment and calibration system for post-fabrication treatment of a phase locked loop charge pump is provided. The adjustment and calibration system includes at least one adjustment circuit, to which a phase locked loop charge pump output is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

    摘要翻译： 提供了一种用于锁相环电荷泵的后制造处理的调整和校准系统。 调节和校准系统包括至少一个调节电路，锁相环电荷泵输出响应于该调节电路;以及存储装置，其选择性地存储与调节电路的状态相关联的控制信息（1）和/或（2） 从将存储在存储装置中的控制信息写入存储装置的测试者，随后选择性地读出，以便将调节电路调整到与控制信息相对应的状态。

    Calibration technique for delay locked loop leakage current
    3.
    发明授权
    Calibration technique for delay locked loop leakage current 有权
    延迟锁定环路漏电流的校准技术

    公开(公告)号：US06614287B1

    公开(公告)日：2003-09-02

    申请号：US10217926

    申请日：2002-08-13

    申请人： Claude R. Gauthier ,  Pradeep Trivedi ,  Brian W. Amick ,  Dean Liu

    发明人： Claude R. Gauthier ,  Pradeep Trivedi ,  Brian W. Amick ,  Dean Liu

    IPC分类号： H03K2100

    CPC分类号： H03L7/0812 ,  H03L7/0891

    摘要： A method and apparatus for post-fabrication calibration and adjustment of a delay locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the leakage current may be stored and subsequently read to adjust the delay locked loop.

    摘要翻译： 提供了用于制造后校准和调整延迟锁定环路漏电流的方法和装置。 校准和调整系统包括调整电路，调整漏电流补偿电路以补偿电容器的漏电流。 电容器连接到延迟锁定环路的控制电压。 在延迟锁定环路中的这种对漏电流的控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。 可以存储泄漏电流期望的调整量的代表值，随后读取以调整延迟锁定环。

    Calibration technique for phase locked loop leakage current
    4.
    发明授权
    Calibration technique for phase locked loop leakage current 有权
    锁相环漏电流校准技术

    公开(公告)号：US06998887B2

    公开(公告)日：2006-02-14

    申请号：US10222648

    申请日：2002-08-16

    申请人： Claude R. Gauthier ,  Brian W. Amick ,  Pradeep Trivedi

    发明人： Claude R. Gauthier ,  Brian W. Amick ,  Pradeep Trivedi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0893 ,  H03L7/18

    摘要： A method and apparatus for post-fabrication calibration and adjustment of a phase locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated. A representative value of the amount of compensation desired in the leakage current may be stored and subsequently read to adjust the phase locked loop.

    摘要翻译： 提供了用于后制造校准和调节锁相环漏电流的方法和装置。 校准和调整系统包括调整电路，调整漏电流补偿电路以补偿电容器的漏电流。 电容器连接到锁相环的控制电压。 在锁相环中的泄漏电流的这种控制允许设计者在制造了锁相环之后实现期望的锁相环工作特性。 泄漏电流期望的补偿量的代表值可以被存储并随后被读取以调整锁相环。

    Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop
    5.
    发明授权
    Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop 有权
    用于校准自偏置锁相环的后制造偏置电压调谐特征的方法和装置

    公开(公告)号：US06753740B2

    公开(公告)日：2004-06-22

    申请号：US10147593

    申请日：2002-05-17

    申请人： Claude Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

    发明人： Claude Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

    IPC分类号： H03B100

    CPC分类号： H03L7/0893 ,  H03L7/18

    摘要： A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

    摘要翻译： 提供了一种用于锁相环偏置发生器的后制造控制的校准和调节系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造了锁相环之后实现期望的锁相环性能特性。 可以存储和随后读取偏置发生器输出中期望的调节量的代表值来调整锁相环。

    Method and apparatus to store delay locked loop biasing parameters
    6.
    发明授权
    Method and apparatus to store delay locked loop biasing parameters 有权
    存储延迟锁定环偏置参数的方法和装置

    公开(公告)号：US07251305B2

    公开(公告)日：2007-07-31

    申请号：US10147838

    申请日：2002-05-17

    申请人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0812

    摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

    摘要翻译： 提供了一种用于延迟锁定环偏置发生器的后制造控制的校准和调整系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。 可以存储和随后读取偏置 - 发生器输出中期望的调节量的代表值来调整延迟锁定环。

    Delay locked loop design with switch for loop filter capacitance leakage current control
    8.
    发明授权
    Delay locked loop design with switch for loop filter capacitance leakage current control 有权
    延迟锁定环路设计，带开关用于环路滤波器电容漏电流控制

    公开(公告)号：US06597219B1

    公开(公告)日：2003-07-22

    申请号：US10199422

    申请日：2002-07-19

    申请人： Pradeep Trivedi ,  Claude R. Gauthier ,  Dean Liu

    发明人： Pradeep Trivedi ,  Claude R. Gauthier ,  Dean Liu

    IPC分类号： H03L706

    CPC分类号： H03L7/0891 ,  H03L7/0812

    摘要： A delay locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the delay locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the delay locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.

    摘要翻译： 提供了延迟锁定环设计，其使用可操作地连接到环路滤波电容器的开关来控制环路滤波电容器的漏电流。 通过将开关与环路滤波电容器串联定位，可以通过在延迟锁定环路的电荷泵“开”时切换开关“开”来控制环路滤波电容器的漏电流，并将开关“关闭” 当电荷泵“关闭”时，累积减少环路滤波电容器漏电流的吞吐量延迟锁定环路的运行。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的延迟锁定环行为。

    System and method for in-situ signal delay measurement for a microprocessor
    9.
    发明授权
    System and method for in-situ signal delay measurement for a microprocessor 有权
    微处理器原位信号延迟测量的系统和方法

    公开(公告)号：US06954913B2

    公开(公告)日：2005-10-11

    申请号：US10407531

    申请日：2003-04-03

    申请人： Claude R. Gauthier ,  Pradeep Trivedi

    发明人： Claude R. Gauthier ,  Pradeep Trivedi

    IPC分类号： G01R31/317 ,  G06F17/50

    CPC分类号： G01R31/31725

    摘要： A system and method of determining an in-situ signal path delay on an integrated circuit. The system and method includes inputting a first signal to a first input node of a first signal path and inputting a second signal to a second input node of a reference signal path. A phase of the first signal output from a first output node of the first signal path is compared to a phase of the second signal output from a second output node of the reference signal path. A phase error signal is output.

    摘要翻译： 一种确定集成电路上原位信号路径延迟的系统和方法。 该系统和方法包括将第一信号输入到第一信号路径的第一输入节点并将第二信号输入到参考信号路径的第二输入节点。 将从第一信号路径的第一输出节点输出的第一信号的相位与从参考信号路径的第二输出节点输出的第二信号的相位进行比较。 输出相位误差信号。

    Phase locked loop design with switch for loop filter capacitance leakage current control
    10.
    发明授权
    Phase locked loop design with switch for loop filter capacitance leakage current control 有权
    锁相环设计，带开关环路滤波器电容漏电流控制

    公开(公告)号：US06570422B1

    公开(公告)日：2003-05-27

    申请号：US10199421

    申请日：2002-07-19

    申请人： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude R. Gauthier

    发明人： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude R. Gauthier

    IPC分类号： H03L706

    CPC分类号： H03L7/18 ,  H03L7/0891

    摘要： A phase locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the phase locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the phase locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

    摘要翻译： 提供了一种锁相环设计，其使用可操作地连接到环路滤波电容器的开关来控制环路滤波电容器的漏电流。 通过将开关与环路滤波电容器串联定位，可以通过在锁相环的电荷泵“开”时切换开关“开”来控制环路滤波电容器的漏电流，并将开关“断开” 当电荷泵“关闭”时，累积降低了环路滤波电容器的泄漏电流，达到了锁相环的运行。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的锁相环行为。