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36 条记录 (耗时 0.015 秒)

    Transmission gate based signal transition accelerator
    1.
    发明授权
    Transmission gate based signal transition accelerator 有权
    基于传输门限的信号转换加速器

    公开(公告)号：US06784689B2

    公开(公告)日：2004-08-31

    申请号：US10068671

    申请日：2002-02-06

    申请人： Sudhakar Bobba ,  Pradeep Trivedi

    发明人： Sudhakar Bobba ,  Pradeep Trivedi

    IPC分类号： H03K1716

    CPC分类号： H04L25/242 ,  H03K5/12 ,  H03K19/01707

    摘要： A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

    摘要翻译： 提供加速信号上的信号转换的负阻抗器件。 负阻抗器件对信号的高到低和低到高的转变都是高度响应的，并且当这些类型的转换之一在信号上开始发生时，负阻抗器件感测到转换并且迅速地将信号驱动到预期 在信号将达到预期值的时间点之前的值未被使用的负阻抗器件。 此外，提供了降低信号上升和下降时间的信号转换加速器设计。 此外，提供了一种加速信号转换的方法。

    Dynamic modulation of on-chip supply voltage for low-power design
    2.
    发明授权
    Dynamic modulation of on-chip supply voltage for low-power design 有权
    低功耗设计的片上电源动态调制

    公开(公告)号：US06737844B2

    公开(公告)日：2004-05-18

    申请号：US10156583

    申请日：2002-05-28

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： G05F1565

    CPC分类号： G11C5/147

    摘要： A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.

    摘要翻译： 一种调制电路，被配置为调制来自第一电源电网的第一电压以产生不大于第二电源网格上的第一电压的期望的第二电压。 数字寄存器可操作地连接到调制电路以确定第二电源电网上的期望的第二电压。 此外，数字寄存器保持代表连接到第二电源网格的电路的活动水平或预期活动水平的值。 调制电路通过在电容之间传送电荷来维持连接到第二电源电网的电路的期望的第二电压。

    Decoupling capacitance assignment technique with minimum leakage power
    3.
    发明授权
    Decoupling capacitance assignment technique with minimum leakage power 有权
    以最小漏电功率去耦电容分配技术

    公开(公告)号：US06694493B2

    公开(公告)日：2004-02-17

    申请号：US09992515

    申请日：2001-11-14

    申请人： Sudhakar Bobba ,  Tyler Thorp

    发明人： Sudhakar Bobba ,  Tyler Thorp

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method and apparatus for assigning decoupling capacitors on an integrated circuit such that leakage power is minimized is provided. Particularly, the method and apparatus use an available capacitance area of an integrated circuit, a capacitance requirement of the integrated circuit, an available thin-oxide capacitance amount, and an available thick-oxide capacitance amount to generate an assignment that indicates what percentage of the available capacitance area should be filled with thin-oxide capacitors and what percentage of the available capacitance area should be filled with thick-oxide capacitors in order to meet the capacitance requirement and minimize leakage power attributable to the thin-oxide and thick-oxide capacitors.

    摘要翻译： 一种用于在集成电路上分配去耦电容器的方法和装置，使得漏电功率最小化。 特别地，该方法和装置使用集成电路的可用电容区域，集成电路的电容需求，可用的薄氧化物电容量和可用的厚氧化物电容量，以产生指示哪个百分比的 应填充薄膜电容器，用厚氧化物电容填充可用电容面积百分比，以满足电容要求，并最大限度地减少归结于薄氧化物和厚氧化物电容器的漏电功率。

    Multiple supply voltage dynamic logic
    4.
    发明授权
    Multiple supply voltage dynamic logic 有权
    多电源电压动态逻辑

    公开(公告)号：US06646473B1

    公开(公告)日：2003-11-11

    申请号：US10170845

    申请日：2002-06-13

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963 ,  H03K19/0016

    摘要： A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

    摘要翻译： 提供能够以正常功耗模式和至少一个降低的功耗模式操作的动态电路。 动态电路可操作地连接到正常电源电压和降低的电源电压，并且能够在正常电源电压和正常频率或降低的电源电压和降低的频率下操作。 通过使用这样的动态电路，可以选择性地控制功率消耗，以便减少不必要的功耗。

    90 degree bump placement layout for an integrated circuit power grid
    6.
    发明授权
    90 degree bump placement layout for an integrated circuit power grid 有权
    集成电路电网的90度凸块布局布局

    公开(公告)号：US06541873B1

    公开(公告)日：2003-04-01

    申请号：US09997523

    申请日：2001-11-29

    申请人： Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

    发明人： Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

    IPC分类号： H01L2348

    CPC分类号： G06F17/5068 ,  H01L23/528 ,  H01L23/5286 ,  H01L2224/16225

    摘要： A 90 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 90 degree bump placement structures is provided.

    摘要翻译： 提供集成电路电网的90度凸块布局布局。 这种布局提高了集成电路的性能和可靠性，并为集成电路设计人员增加了设计集成电路的灵活性和均匀性。 此外，提供了具有多个90度凸块放置结构的集成电路的顶部金属层的图案化凸块阵列。

    Phase locked loop design with diode for loop filter capacitance leakage current control
    8.
    发明授权
    Phase locked loop design with diode for loop filter capacitance leakage current control 有权
    具有二极管的锁相环设计，用于环路滤波器电容漏电流控制

    公开(公告)号：US06861885B2

    公开(公告)日：2005-03-01

    申请号：US10199426

    申请日：2002-07-19

    申请人： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

    发明人： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

    IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/06

    CPC分类号： H03L7/093 ,  H03L7/0891 ,  Y10S331/02

    摘要： A phase locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

    摘要翻译： 锁相环设计使用可操作地连接到环路滤波电容器的二极管来控制环路滤波电容器的漏电流。 通过与环路滤波电容串联定位二极管，减小环路滤波电容两端的电压电位，从而减小环路滤波电容的漏电流。 此外，环路滤波电容器的漏电流被控制为不能超过二极管的电流。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的锁相环行为。

    Increasing implicit decoupling capacitance using asymmetric shieldings
    10.
    发明授权
    Increasing implicit decoupling capacitance using asymmetric shieldings 有权
    使用不对称屏蔽增加隐式去耦电容

    公开(公告)号：US06653857B2

    公开(公告)日：2003-11-25

    申请号：US10000676

    申请日：2001-10-31

    申请人： Sudhakar Bobba ,  Tyler Thorp

    发明人： Sudhakar Bobba ,  Tyler Thorp

    IPC分类号： H03K1716

    CPC分类号： H04L25/08 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetrically shielding to increase performance is provided. Further, a method for increasing an amount of implicit decoupling capacitance on a circuit through asymmetric shielding is provided. Further, a method to increase component performance by increasing implicit decoupling capacitance is provided.

    摘要翻译： 提供了一种非对称屏蔽信号以增加去耦电容的集成电路。 基于信号处于特定值的概率，信号被不对称地屏蔽。 此外，提供了使用不对称屏蔽来提高性能的计算机系统。 此外，提供了一种通过非对称屏蔽增加电路上的隐式去耦电容量的方法。 此外，提供了通过增加隐式解耦电容来增加组件性能的方法。