公开(公告)号：US07626845B2

公开(公告)日：2009-12-01

申请号：US11610284

申请日：2006-12-13

申请人： Clinton H. Holder, Jr. ,  Kang W. Lee ,  Joseph E. Simko ,  Yehuda Smooha ,  Ying Zhu

发明人： Clinton H. Holder, Jr. ,  Kang W. Lee ,  Joseph E. Simko ,  Yehuda Smooha ,  Ying Zhu

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

摘要翻译： 在一个实施例中，本发明是包括OTP存储器和调节电路的集成电路（IC）。 IC接收外部产生的直流编程电压信号，调理电路变换为用于编程OTP存储器的编程脉冲信号。 调节电路包括：（i）复位保护电路，用于在IC上电时保持编程脉冲信号为低电平，（ii）过压保护电路，用于基本上防止编程脉冲电压超出预定义的边界，以及（iii）转换 用于控制编程脉冲电压的开关。 如果使能信号为开，编程脉冲电压为（i）基本上等于外部产生的直流电压，以及（ii）如果使能信号关闭，则基本上等于参考电压。

公开(公告)号：US20080144350A1

公开(公告)日：2008-06-19

申请号：US11610284

申请日：2006-12-13

申请人： Clinton H. Holder ,  Kang W. Lee ,  Joseph E. Simko ,  Yehuda Smooha ,  Ying Zhu

发明人： Clinton H. Holder ,  Kang W. Lee ,  Joseph E. Simko ,  Yehuda Smooha ,  Ying Zhu

IPC分类号： G11C17/08

CPC分类号： G11C17/16 ,  G11C17/18

摘要： In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

摘要翻译： 在一个实施例中，本发明是包括OTP存储器和调节电路的集成电路（IC）。 IC接收外部产生的直流编程电压信号，调理电路变换为用于编程OTP存储器的编程脉冲信号。 调节电路包括：（i）复位保护电路，用于在IC上电时保持编程脉冲信号为低电平，（ii）过压保护电路，用于基本上防止编程脉冲电压超出预定义的边界，以及（iii）转换 用于控制编程脉冲电压的开关。 如果使能信号为开，编程脉冲电压为（i）基本上等于外部产生的直流电压，以及（ii）如果使能信号关闭，则基本上等于参考电压。

公开(公告)号：US07034653B2

公开(公告)日：2006-04-25

申请号：US10768771

申请日：2004-01-30

申请人： Dipankar Bhattacharya ,  John Christopher Kriz ,  Stefan Allen Siegel ,  Joseph E. Simko ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  John Christopher Kriz ,  Stefan Allen Siegel ,  Joseph E. Simko ,  Yehuda Smooha

IPC分类号： H01C1/01

CPC分类号： H01L28/20 ,  H01C1/14 ,  H01L23/5228 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.

摘要翻译： 半导体电阻器包括形成在半导体衬底上的电阻体和在其两端电连接到电阻体的第一和第二导电端子。 半导体电阻器还包括在第一和第二导电端子和电阻器主体中的至少一个之间的至少第一和第二导电路径。 至少一个导电端子被配置为使得至少第一和第二导电路径之间的至少一个导电端子的电阻基本上与至少第一和第二导电路径之间的电阻体的电阻相匹配。 以这种方式，至少第一和第二导电路径之间的电流分布基本匹配。

公开(公告)号：US07397279B2

公开(公告)日：2008-07-08

申请号：US11342175

申请日：2006-01-27

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Joseph E. Simko

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Joseph E. Simko

IPC分类号： H03K19/0175 ,  H03K5/00

CPC分类号： H03K19/017509 ,  H03K3/356104

摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

摘要翻译： 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，该输入级包括至少一个具有第一阈值电压 相关联。 电压电平转换器电路还包括锁存电路，其操作以存储表示输入信号的逻辑状态的信号，所述锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，所述第二阈值电压大于 第一阈值电压。 电压钳位电路连接在输入级和锁存电路之间。 电压钳位电路用于限制输入级两端的电压，输入级两端的电压幅度作为第一和第二电压源之间的电压差的函数被控制。

公开(公告)号：US06992489B2

公开(公告)日：2006-01-31

申请号：US10776778

申请日：2004-02-11

申请人： Dipankar Bhattacharya ,  John Christopher Kriz ,  Joseph E. Simko

发明人： Dipankar Bhattacharya ,  John Christopher Kriz ,  Joseph E. Simko

IPC分类号： G01R19/26 ,  G01R19/257

CPC分类号： G01R19/16595 ,  G01R19/16519

摘要： A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.

摘要翻译： 可配置为指示施加到电路的输入信号的电压电平的电路包括至少一个晶体管，其具有连接到第一电压源的第一端子，被配置为接收输入信号的第二端子，以及可操作地耦合到 输出电路。 电路还包括连接在晶体管的第三端子和第二电压源之间的无源负载。 电路被配置为在电路的输出处产生输出信号。 输出信号处于第一值表示输入信号基本上处于第一电压电平，并且输出信号处于第二值表示输入信号基本上处于第二电压电平。