公开(公告)号：US10901900B2

公开(公告)日：2021-01-26

申请号：US14394982

申请日：2013-04-12

申请人： Commissariat a l'energie atomique et aux ene alt ,  BULL SAS

发明人： Christian Bernard ,  Eric Guthmuller ,  Huy Nam Nguyen

IPC分类号： G06F12/08 ,  G06F12/0817 ,  G06F12/0813

摘要： A cache coherence management system includes: a set of directories distributed between nodes of a network for interconnecting processors including cache memories, each directory including a correspondence table between cache lines and information fields on the cache lines; and a mechanism updating the directories by adding, modifying, or deleting cache lines in the correspondence tables. In each correspondence table and for each cache line identified, at least one field is provided for indicating a possible blocking of a transaction relative to the cache line considered, when the blocking occurs in the node associated with the correspondence table considered. The system further includes a mechanism detecting fields indicating a transaction blocking and restarting each transaction detected as blocked from the node in which it is indicated as blocked.

公开(公告)号：US09542317B2

公开(公告)日：2017-01-10

申请号：US14408402

申请日：2013-06-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  BULL SAS

发明人： Christian Bernard ,  Eric Guthmuller ,  Huy Nam Nguyen

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F11/34

CPC分类号： G06F12/0822 ,  G06F11/3409 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/084 ,  G06F2212/154 ,  G06F2212/254 ,  G06F2212/283 ,  G06F2212/622

摘要： A system for data processing with management of a cache consistency in a network of processors including cache memories, the network including plural nodes for access to a main memory interconnected with one another, a set of directories being distributed between nodes of the network, each directory including a table of correspondence between cache lines and information fields on the cache lines. The system includes a first sub-network for interconnection of the nodes with one another, implementing a first message transmission protocol providing read/write access to the directories during any passage in the corresponding nodes of a message passing through the first sub-network, and a second sub-network for interconnection of the nodes with one another, implementing a second message transmission protocol, the second protocol excluding any read/write access to the directories during any passage in the corresponding nodes of a message passing through the second sub-network.

摘要翻译： 一种用于通过管理包括高速缓存存储器的处理器网络中的高速缓存一致性的数据处理系统，所述网络包括用于访问彼此互连的主存储器的多个节点，分布在网络节点之间的一组目录，每个目录 包括高速缓存行和缓存行上的信息字段之间的对应关系表。 该系统包括用于互连节点的第一子网络，实现在通过第一子网络的消息的相应节点中的任何通过期间提供对目录的读/写访问的第一消息传输协议，以及 第二子网络，用于将节点彼此互连，实现第二消息传输协议，第二协议在通过第二子网的消息的相应节点中的任何通过期间，排除对目录的任何读/写访问 。

公开(公告)号：US20150242318A1

公开(公告)日：2015-08-27

申请号：US14408402

申请日：2013-06-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  BULL SAS

发明人： Christian Bernard ,  Eric Guthmuller ,  Huy Nam Nguyen

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F11/3409 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/084 ,  G06F2212/154 ,  G06F2212/254 ,  G06F2212/283 ,  G06F2212/622

摘要： A system for data processing with management of a cache consistency in a network of processors including cache memories, the network including plural nodes for access to a main memory interconnected with one another, a set of directories being distributed between nodes of the network, each directory including a table of correspondence between cache lines and information fields on the cache lines. The system includes a first sub-network for interconnection of the nodes with one another, implementing a first message transmission protocol providing read/write access to the directories during any passage in the corresponding nodes of a message passing through the first sub-network, and a second sub-network for interconnection of the nodes with one another, implementing a second message transmission protocol, the second protocol excluding any read/write access to the directories during any passage in the corresponding nodes of a message passing through the second sub-network.

摘要翻译： 一种用于通过管理包括高速缓存存储器的处理器网络中的高速缓存一致性的数据处理系统，所述网络包括用于访问彼此互连的主存储器的多个节点，分布在网络节点之间的一组目录，每个目录 包括高速缓存行和缓存行上的信息字段之间的对应关系表。 该系统包括用于互连节点的第一子网络，实现在通过第一子网络的消息的相应节点中的任何通过期间提供对目录的读/写访问的第一消息传输协议，以及 第二子网络，用于将节点彼此互连，实现第二消息传输协议，第二协议在通过第二子网的消息的相应节点中的任何通过期间，排除对目录的任何读/写访问 。

公开(公告)号：US20150106571A1

公开(公告)日：2015-04-16

申请号：US14394982

申请日：2013-04-12

申请人： Commissariat a l'energie atomique et aux ene alt ,  BULL SAS

发明人： Christian Bernard ,  Eric Guthmuller ,  Huy Nam Nguyen

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0813 ,  G06F12/0817 ,  G06F2212/254 ,  G06F2212/621

摘要： A cache coherence management system includes: a set of directories distributed between nodes of a network for interconnecting processors including cache memories, each directory including a correspondence table between cache lines and information fields on the cache lines; and a mechanism updating the directories by adding, modifying, or deleting cache lines in the correspondence tables. In each correspondence table and for each cache line identified, at least one field is provided for indicating a possible blocking of a transaction relative to the cache line considered, when the blocking occurs in the node associated with the correspondence table considered. The system further includes a mechanism detecting fields indicating a transaction blocking and restarting each transaction detected as blocked from the node in which it is indicated as blocked.

摘要翻译： 高速缓存一致性管理系统包括：分布在网络节点之间的一组目录，用于互连包括高速缓存存储器的处理器，每个目录包括高速缓存行和缓存行上的信息字段之间的对应表; 以及通过在对应表中添加，修改或删除高速缓存行来更新目录的机制。 在每个对应表和对于所识别的每个高速缓存行中，当与所考虑的对应表相关联的节点中发生阻塞时，提供至少一个字段用于指示事务相对于所考虑的高速缓存行的可能的阻塞。 该系统还包括机构，其检测指示事务阻塞的字段，并且从被指示为被阻止的节点重新启动被检测为被阻止的每个事务。