公开(公告)号：US20060218449A1

公开(公告)日：2006-09-28

申请号：US11085599

申请日：2005-03-22

申请人： Conrado Blasco Allue ,  Stephen Hill ,  Richard Slobodnik

发明人： Conrado Blasco Allue ,  Stephen Hill ,  Richard Slobodnik

IPC分类号： G06F11/00

CPC分类号： G11C29/16 ,  G01R31/31705 ,  G01R31/31722 ,  G01R31/31723 ,  G11C29/08 ,  G11C2029/0401

摘要： A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

摘要翻译： 数据处理装置可以在自检模式或操作模式中操作。 所述设备包括多个功能单元，所述功能单元中的至少一个可操作以执行数据处理操作，并且所述多个功能单元的至少一个子集具有用于存储配置数据的相应协处理器寄存器中的至少一个， 用于存储调试数据的相应调试寄存器和相应的功能单元存储器。 一种存储器自检控制器，其可在自检模式下操作以输出用于执行存取操作的自检数据，以确认功能单元存储器的正确操作。 调试控制器输出调试数据并协调调试操作，调试控制器是多个功能单元之一。 在操作模式中，配置环总线提供用于在多个功能单元的第一环序列之间通信配置指令的环路，而调试环总线提供用于在第二环序列之间通信调试数据的环路 的多个功能单元。 第一环序列与第二环序列相同，数据处理装置在自检模式下可操作以耦合配置环总线和调试环总线，以提供用于通信自检数据的组合数据路径 在多个功能单元之间。

公开(公告)号：US20060200653A1

公开(公告)日：2006-09-07

申请号：US11072644

申请日：2005-03-07

申请人： Conrado Blasco Allue ,  Glen Harris ,  Stephen Hill

发明人： Conrado Blasco Allue ,  Glen Harris ,  Stephen Hill

IPC分类号： G06F9/44

CPC分类号： G06F9/3822 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/382 ,  G06F9/3875

摘要： Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.

摘要翻译： 在支持预测指令的多指令流水线数据处理系统中，在假定它们被预测的情况下，程序指令最初被解码。 当检测到预测指令时，在指令解码器级内产生预测信号。 然后可以使用该预测信号的存在或不存在来校正已经基于假定程序指令被预测的方式执行的任何解码。 预测指令可以说明可变数量的以下指令。 预测指令可以与其所预测的指令并行地发出，然而在至少对其他程序指令进行了一些解码之前，不需要确认预测指令的正确识别。

公开(公告)号：US20070033383A1

公开(公告)日：2007-02-08

申请号：US11197521

申请日：2005-08-05

申请人： Conrado Blasco Allue ,  Glen Harris ,  Stephen Hill

发明人： Conrado Blasco Allue ,  Glen Harris ,  Stephen Hill

IPC分类号： G06F9/40

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30196

摘要： A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit. Accordingly, this can significantly reduce the amount of logic duplicated in the decoder units which, in turn, reduces the amount chip area required to support decoding and reduces power consumption. Also, since the decode units are no longer required to support the decoding of such a high number of different instructions, the complexity of each decode unit can be reduced, which can result in increased performance during decode.

摘要翻译： 一种可操作以处理来自多个指令集的指令的方法和数据处理装置，所述多个指令集各自共享公共指令的子集，并且每个具有剩余指令集。 数据处理装置包括：多个解码单元，每个解码单元可操作以仅从所述多个指令集中的相应一个指令集解码所述剩余指令集; 以及公共解码单元，用于从多个指令集中的每一个解码多个公共指令的子集。 这使得来自每个指令集的公共指令由公共解码单元解码。 因此，可以从这些解码单元中删除否则将在每个指令集的各个解码单元中复制的逻辑，并且在公共解码单元中仅提供一次。 因此，这可以显着减少在解码器单元中复制的逻辑量，这反过来减少了支持解码所需的芯片面积的数量并降低功耗。 此外，由于不再需要解码单元来支持这么多数量的不同指令的解码，因此可以减少每个解码单元的复杂度，这可以导致在解码期间增加的性能。

公开(公告)号：US20070050600A1

公开(公告)日：2007-03-01

申请号：US11205310

申请日：2005-08-17

申请人： Stephen Hill ,  Glen Harris ,  David Williamson

发明人： Stephen Hill ,  Glen Harris ,  David Williamson

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3857 ,  G06F11/3636 ,  G06F11/3656

摘要： Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data processing apparatus comprises: decode/issue logic operable to receive and decode an instruction to be processed by the data processing apparatus and to determine when to issue a decoded instructions for execution by execution logic; execution logic operable to execute the decoded instructions; interface logic selectively operable to receive trace information relating to the state of the data processing apparatus generated in response to execution of the decoded instructions for transmission to trace monitoring infrastructure; and throttle logic operable to predict whether issuing the decoded instruction to the execution logic for execution would be likely to cause the trace information to be transmitted to said trace monitoring infrastructure to exceed a capacity of said trace monitoring infrastructure and, if so, to prevent the decode/issue logic from issuing the decoded instruction to the execution logic. Accordingly, the throttle logic reviews each instruction to be executed and predicts whether issuing that instruction at that time will or is likely to cause the capacity to be exceeded. In the event that the throttle logic determines that the capacity is likely to be exceeded, the instruction is prevented from being issued to the execution logic which reduces the likelihood that any state information is lost.

摘要翻译： 公开了用于防止通过迹线基础设施传输的跟踪信息丢失的技术。 提供了一种处理指令的数据处理装置。 数据处理装置包括：解码/发布逻辑，可操作以接收和解码由数据处理装置处理的指令，并确定何时发出经执行逻辑执行的解码指令; 执行逻辑，用于执行解码指令; 接口逻辑选择性地可操作以接收与响应于解码指令的执行而生成的数据处理设备的状态相关的跟踪信息，以便传输到跟踪监视基础设施; 并且可操作以用于预测是否向执行逻辑发出解码指令以进行执行的油门逻辑可能导致跟踪信息被发送到所述跟踪监视基础设施以超过所述跟踪监视基础设施的容量，如果是，则阻止 解码/发布逻辑从解码指令发出到执行逻辑。 因此，节气门逻辑检查要执行的每个指令，并且预测当时是否发出该指令将或可能导致超过容量。 在节气门逻辑确定容量可能被超过的情况下，防止指令被发送到执行逻辑，这减少了任何状态信息丢失的可能性。

公开(公告)号：US20060211045A1

公开(公告)日：2006-09-21

申请号：US10551475

申请日：2004-03-31

申请人： Michael George ,  Stephen Hill ,  Barrie Kellam ,  Richard Middleton

发明人： Michael George ,  Stephen Hill ,  Barrie Kellam ,  Richard Middleton

IPC分类号： C40B40/04 ,  C40B40/10

CPC分类号： C07D209/56 ,  C07D333/02 ,  C07D473/00 ,  C07H19/16 ,  C07H19/20 ,  C40B20/04 ,  C40B30/04 ,  C40B40/04 ,  C40B50/08 ,  C40B70/00 ,  G01N33/533

摘要： Library comprising a plurality of tagged non-peptide ligands of formula I (LigJL)mL(JTTag)m(JTL(JLLig)m)p including and salts thereof comprising one or a plurality of same or different ligand moieties Lig each linked to a one or a plurality of same or different tag moieties Tag via same or different linker moieties L and same or different linking site or linking functionality JT and JL wherein Lig comprises a GPCR ligand, an inhibitor of an intracellular enzyme or a substrate or inhibitor of a drug transporter; L is a single bond or is any linking moiety selected from a heteroatom such as N, O, S, P, branched or straight chain saturated or unsaturated, optionally heteroatom containing, C1-600 hydrocarbyl and combinations thereof, which may be monomeric, oligomeric having oligomeric repeat of 2 to 30 or polymeric having polymeric repeat in excess of 30 up to 300; Tag is any known or novel tagging substrate; m are each independently selected from a whole number integer from 1 to 3; p is 0 to 3 characterised in that linking is at same or different linking sites in compounds comprising different Lig, JL, L JT and/or -Tag and is at different linking sites in compounds comprising same Lig, JL, L JT and/or -Tag; process for the preparation thereof; process for the preparation of a library compound of formula I or a precursor of formula IV; method for selecting a compound of formula I from a library thereof; compound of formula I associated with information relating to its pharmacological properties; a novel compound of formula I or precursor of formula IV; uses thereof; methods for binding or inhibition therewith; use of a fluorescent target therewith; a modified cell surface GPCR and cells expressing the same; and a kit comprising a compound of formula I and a target therefor.

公开(公告)号：US20050280871A1

公开(公告)日：2005-12-22

申请号：US11145021

申请日：2005-06-03

申请人： Pier Gardella ,  Massimiliano Barone ,  Gary Sweet ,  Danilo Pau ,  Stephen Hill ,  Simon Goda

发明人： Pier Gardella ,  Massimiliano Barone ,  Gary Sweet ,  Danilo Pau ,  Stephen Hill ,  Simon Goda

IPC分类号： G06T3/40 ,  G09G3/20 ,  G09G5/02 ,  H04N1/40 ,  H04N1/41 ,  H04N1/64 ,  H04N7/26 ,  H04N1/52 ,  H04N1/405

CPC分类号： H04N19/00 ,  G09G3/2051 ,  G09G5/02 ,  H04N1/40087 ,  H04N19/42 ,  H04N19/90

摘要： A dither matrix is applied to a high-resolution image to compare the value of each of the pixels that compose it with a threshold value of the matrix and to obtain an output value of the matrix (Dither matrix value) from each comparison. To each pixel value of the image there is applied an algorithm involving simple but displacement operation, namely shifts to the left and shifts to the right. The pixel values of a low-resolution image are output from the applied algorithm.

摘要翻译： 将抖动矩阵应用于高分辨率图像，以将构成它的每个像素的值与矩阵的阈值进行比较，并从每个比较中获得矩阵（抖动矩阵值）的输出值。 对于图像的每个像素值，应用涉及简单但位移操作的算法，即向左移动并向右移动。 从应用的算法输出低分辨率图像的像素值。

公开(公告)号：US20140119863A1

公开(公告)日：2014-05-01

申请号：US14118020

申请日：2012-05-17

申请人： Stephen Hill ,  Hilary Anna Thornley

发明人： Stephen Hill ,  Hilary Anna Thornley

IPC分类号： B60P1/43

CPC分类号： B60P1/43 ,  A01K1/0272 ,  A01K1/035 ,  B60P3/04

摘要： A reconfigurable vehicle partition for compartmentalising a space within a vehicle is disclosed. The partition comprises a frame which is arranged to extend within an interior of the vehicle and which is arranged to support a gate, the gate comprising a plurality of pivotally interconnected panels which are reconfigurable between a folded gate configuration and an unfolded gate configuration. The gate is arranged to pivot with respect to the frame between a closed configuration in which the gate extends substantially within the frame to partition the vehicle, and an open configuration, in which the gate extends out of the plane of the frame. In the closed configuration, the gate is arranged to extend across the frame in a substantially folded configuration, and in the open configuration the gate is arranged to extend out of the plane of the frame in the unfolded configuration to provide a ramp access into and out from the vehicle.

摘要翻译： 公开了一种用于区分车辆内的空间的可重构车辆隔板。 隔板包括框架，该框架布置成在车辆内部延伸并且被布置成支撑门，该门包括多个可枢转地互连的面板，其可在折叠门构型和未折叠门构型之间重构。 门被布置成相对于框架枢转，在闭合构型之间，其中门基本上在框架内延伸以分隔车辆;以及打开构型，其中门延伸出框架的平面。 在闭合配置中，门被布置成以基本上折叠的构造延伸穿过框架，并且在打开构造中，门布置成在展开构型中延伸出框架的平面以提供斜坡进入和退出 从车上。

公开(公告)号：US08115780B2

公开(公告)日：2012-02-14

申请号：US11655051

申请日：2007-01-18

申请人： Simon Goda ,  Stephen Hill

发明人： Simon Goda ,  Stephen Hill

IPC分类号： G09G5/00

CPC分类号： G06T15/503 ,  G06T11/40 ,  G06T2200/12

摘要： A system and method for generating an image on a display. The display includes a plurality of pixels from a vector description of a scene. The data is sampled from the vector description to provide data samples at locations defined in relation to the pixels. For example, the locations may include a first and second locations at the edges of the pixels, a third location at the corner of the pixels and a fourth location at the center of the pixels. The data samples are stored in a buffer and processed for each of the pixels to give an averaged data value. The image is then generated the image on the display by applying the averaged data value to each of the pixels. The calculation of the weighted averaged color value is repeated for each of the fragments in the buffer until all of the samples have been averaged.

摘要翻译： 一种用于在显示器上生成图像的系统和方法。 显示器包括来自场景的向量描述的多个像素。 从矢量描述中采样数据，以在与像素相关的位置定义的位置提供数据样本。 例如，位置可以包括在像素的边缘处的第一和第二位置，在像素的角落处的第三位置和在像素的中心处的第四位置。 将数据样本存储在缓冲器中并针对每个像素进行处理以给出平均数据值。 然后，通过将平均数据值应用于每个像素，在图像上生成图像。 对缓冲器中的每个片段重复加权平均颜色值的计算，直到所有样本已经被平均。

公开(公告)号：US07623270B2

公开(公告)日：2009-11-24

申请号：US11145021

申请日：2005-06-03

申请人： Pier Luigi Gardella ,  Massimiliano Barone ,  Gary Sweet ,  Danilo Pau ,  Stephen Hill ,  Simon Goda

发明人： Pier Luigi Gardella ,  Massimiliano Barone ,  Gary Sweet ,  Danilo Pau ,  Stephen Hill ,  Simon Goda

IPC分类号： H04N1/52 ,  H04N1/405 ,  G09G5/02

CPC分类号： H04N19/00 ,  G09G3/2051 ,  G09G5/02 ,  H04N1/40087 ,  H04N19/42 ,  H04N19/90

摘要： A dither matrix is applied to a high-resolution image to compare the value of each of the pixels that compose it with a threshold value of the matrix and to obtain an output value of the matrix (Dither matrix value) from each comparison. To each pixel value of the image there is applied an algorithm involving simple but displacement operation, namely shifts to the left and shifts to the right. The pixel values of a low-resolution image are output from the applied algorithm.

摘要翻译： 将抖动矩阵应用于高分辨率图像，以将构成它的每个像素的值与矩阵的阈值进行比较，并从每个比较中获得矩阵（抖动矩阵值）的输出值。 对于图像的每个像素值，应用涉及简单但位移操作的算法，即向左移动并向右移动。 从应用的算法输出低分辨率图像的像素值。

公开(公告)号：US20070043930A1

公开(公告)日：2007-02-22

申请号：US11204399

申请日：2005-08-16

申请人： Stephen Hill ,  Glen Harris ,  David Williamson

发明人： Stephen Hill ,  Glen Harris ,  David Williamson

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： Techniques for improving the performance of a data processing apparatus are disclosed. A data processing apparatus operable to process instructions and operable to determine, prior to each instruction being issued for execution, when resources associated with that instruction are predicted to be available for use by succeeding instructions is provided. The data processing apparatus comprises scoreboard logic operable to store an indication of when resources associated with an instruction to be issued are predicted to be available for use by succeeding instructions; issue logic operable to determine, by reference to the scoreboard logic, when the instruction can be issued for execution, the issue logic being further operable in the case that the instruction falls within a class of instructions which have been designated as instructions for which it is uncertain when resources associated with those instructions will be available for use by succeeding instructions, to prevent succeeding instructions from issuing until all preceding instructions have been executed; and inhibit override logic operable to detect when the instruction to be issued falls within a sub-class of instructions, to review all preceding instructions and, in the event that the they all fall within the sub-class of instructions, to cause the issue logic to enable the succeeding instruction to be issued for execution even when all preceding instructions have not been completed. Enabling the succeeding instruction to be issued without first draining all the preceding instructions reduces the latency period experienced prior to that instruction being issued. It will be appreciated that this approach can significantly improve the performance of the data processing apparatus.

摘要翻译： 公开了一种用于提高数据处理装置的性能的技术。 一种数据处理装置，可操作以处理指令并且可操作以提供在执行每个指令之前，当与该指令相关联的资源被预测为可供随后的指令使用时。 数据处理装置包括记分板逻辑，其可操作以存储与被发布的指令相关联的资源被预测为可以由后续指令使用的指示; 发出逻辑可操作以通过参考记分板逻辑来确定何时可以发出指令以执行，所述发出逻辑在所述指令落入已被指定为其指令的指令类别的情况下可进一步操作 当与这些指令相关联的资源将可以通过后续指令使用时，不确定，以防止后续指令发出，直到所有先前的指令被执行; 并且禁止超控逻辑可操作以检测什么时候要发出的指令落在指令的子类别内，以检查所有先前的指令，并且在它们都落入指令的子类别的情况下导致发出逻辑 以便即使所有先前的指令尚未完成，也可以执行后续指令以执行。 在不首先排除所有前述指令的情况下启用后续指令将减少发出该指令之前经历的等待时间。 应当理解，该方法可以显着地提高数据处理装置的性能。