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185 条记录 (耗时 0.041 秒)

    Lever control mechanism of a drain valve of a toilet tank
    5.
    发明授权
    Lever control mechanism of a drain valve of a toilet tank 有权
    马桶水箱排水阀的杠杆控制机构

    公开(公告)号：US09032561B2

    公开(公告)日：2015-05-19

    申请号：US13487941

    申请日：2012-06-04

    申请人： Meijuan Chen ,  Xingdong Wang ,  Bing Wang

    发明人： Meijuan Chen ,  Xingdong Wang ,  Bing Wang

    IPC分类号： E03D1/00 ,  E03D5/092

    CPC分类号： E03D5/092 ,  Y10T74/18216

    摘要： A lever control mechanism of a drain valve of a toilet tank has a lever assembly assembled in the wall of the toilet tank and a lever linked to the revolving shaft of the lever assembly. The lever assembly is connected to a deviator, which is disposed with a drive arm; the drive arm is connected to the revolving shaft. The deviator is disposed with a joint portion and at least a leading hole to limit the lever revolving vertically. One end of the lever is run through the leading hole to rotationally connect to the joint portion; the drive arm is revolved by the driving of the revolving shaft to drive the lever revolved in the fan shaped vertical surface limited formed by the joint portion and the leading hole.

    摘要翻译： 马桶水箱的排水阀的杠杆控制机构具有组装在马桶水箱的壁上的杠杆组件和连接到杠杆组件的回转轴的杠杆。 杠杆组件连接到偏移器，该偏移器设置有驱动臂; 驱动臂连接到旋转轴。 偏转器设置有接合部分和至少一个引导孔，以限制杆垂直地旋转。 杆的一端穿过引导孔，以旋转地连接到接合部分; 驱动臂通过旋转轴的驱动旋转，以驱动由接合部分和引导孔形成的扇形垂直表面中旋转的杆。

    Tracking bit cell
    6.
    发明授权
    Tracking bit cell 有权
    跟踪位单元格

    公开(公告)号：US08934308B2

    公开(公告)日：2015-01-13

    申请号：US13273705

    申请日：2011-10-14

    申请人： Bing Wang

    发明人： Bing Wang

    IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C7/22 ,  G11C7/227

    摘要： A memory macro includes a tracking circuit and a plurality of memory cells. The tracking circuit has tracking transistors configured to receive a tracking voltage value. Each memory cell of the plurality of memory cells has memory transistors configured to receive a cell voltage value different from the tracking voltage value. The tracking circuit is configured to generate a tracking signal based on which a reading signal of a memory cell of the plurality of memory cells is generated.

    摘要翻译： 存储器宏包括跟踪电路和多个存储单元。 跟踪电路具有配置成接收跟踪电压值的跟踪晶体管。 多个存储单元的每个存储单元具有被配置为接收与跟踪电压值不同的单元电压值的存储晶体管。 跟踪电路被配置为产生跟踪信号，基于该跟踪信号生成多个存储器单元的存储单元的读取信号。

    Two level cross-correlation based system for watermarking continuous digital media
    7.
    发明授权
    Two level cross-correlation based system for watermarking continuous digital media 有权
    用于水印连续数字媒体的两级互相关系统

    公开(公告)号：US08867781B2

    公开(公告)日：2014-10-21

    申请号：US13460379

    申请日：2012-04-30

    申请人： Shien-Tai Pan ,  Bing Wang ,  Hoai Le ,  Yi Li ,  Victor Kai-Chieh Liang ,  Maurice Chow ,  Richard Thai

    发明人： Shien-Tai Pan ,  Bing Wang ,  Hoai Le ,  Yi Li ,  Victor Kai-Chieh Liang ,  Maurice Chow ,  Richard Thai

    IPC分类号： G06K9/00 ,  G06T1/00 ,  H04N19/48 ,  H04N19/467 ,  H04N19/42

    CPC分类号： G06T1/005 ,  H04N19/42 ,  H04N19/467 ,  H04N19/48

    摘要： A two level cross-correlation based system for watermarking continuous digital media at the system application level. It is a post-compression process for watermarking where no a priori knowledge of the underlying compression algorithm is required. Per each compressed media frame, a current unique digital signature is generated based on the data from the current compressed frame plus the digital signature that has been previously generated. The signature thus generated is then used in conjunction with the next compressed frame to generate the next unique digital signature. All digital signatures are correlated according to the above process until a “reset” signal is issued. A new chain of correlated digital signatures is produced by the system with a predetermined initial signature.

    摘要翻译： 一种基于二级互相关的系统，用于在系统应用级别对连续数字媒体进行水印。 它是用于水印的后压缩过程，其中不需要基础压缩算法的先验知识。 根据每个压缩媒体帧，基于来自当前压缩帧的数据加上先前生成的数字签名生成当前唯一的数字签名。 这样生成的签名然后与下一个压缩帧一起使用，以生成下一个独特的数字签名。 所有数字签名根据上述过程相关，直到发出“复位”信号。 相关数字签名的新链由系统产生具有预定的初始签名。

    Preparation method of rosuvastatin calcium and its intermediates
    8.
    发明授权
    Preparation method of rosuvastatin calcium and its intermediates 有权
    罗苏伐他汀钙及其中间体的制备方法

    公开(公告)号：US08653265B2

    公开(公告)日：2014-02-18

    申请号：US12994520

    申请日：2009-05-27

    申请人： Benshun Chen ,  Bing Wang ,  Xiaofeng Jin ,  Lin Zou

    发明人： Benshun Chen ,  Bing Wang ,  Xiaofeng Jin ,  Lin Zou

    IPC分类号： C07D239/02

    CPC分类号： C07D239/42

    摘要： A preparation method of rosuvastatin calcium (Formula 1), which can be used for the production of medicament lowering the levels of LDL-cholesterol and triglycerides in vivo, is provided. Such preparation method is suitable for industrial production. Furthermore, the intermediate crystallines used in the preparation method are provided.

    摘要翻译： 提供了可用于生产降低LDL-胆固醇和甘油三酯水平的药物的瑞舒伐他汀钙（配方1）的制备方法。 这种制备方法适用于工业生产。 此外，提供了制备方法中使用的中间结晶。

    Two-port SRAM write tracking scheme
    9.
    发明授权
    Two-port SRAM write tracking scheme 有权
    双端口SRAM写入跟踪方案

    公开(公告)号：US08619477B2

    公开(公告)日：2013-12-31

    申请号：US12839624

    申请日：2010-07-20

    申请人： Bing Wang ,  Kuoyuan (Peter) Hsu ,  Derek C. Tao

    发明人： Bing Wang ,  Kuoyuan (Peter) Hsu ,  Derek C. Tao

    IPC分类号： G11C7/10

    CPC分类号： G11C11/419 ,  G11C11/413

    摘要： A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.

    摘要翻译： 静态随机存取存储器（SRAM）包括共享读位线（RBL）和写位线（WBL）的至少两个存储器单元。 每个存储单元耦合到相应的读字线（RWL）和相应的写字线（WWL）。 写跟踪控制电路耦合到存储器单元，以确定存储器单元的写入时间。 写跟踪控制电路能够接收输入电压并提供输出电压。 在写跟踪操作期间，各存储单元的相应RWL和相应的WWL被断言。

    Amplifier sensing
    10.
    发明授权
    Amplifier sensing 有权
    放大器感应

    公开(公告)号：US08339886B2

    公开(公告)日：2012-12-25

    申请号：US13026565

    申请日：2011-02-14

    申请人： Bing Wang

    发明人： Bing Wang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C11/413

    摘要： A circuit comprises a first read bit line, a second read bit line, and a sense amplifier. First and second read bit lines couple a plurality of memory cells and a reference cell of a memory array, respectively. The sense amplifier is configured to receive the first read bit line as a first input and the second read bit line as a second input. When a memory cell of the first plurality of memory cells is read, the memory cell is read activated, the first reference cell is configured to be off, the second reference cell is configured to be on, and the sense amplifier is configured to provide an output reflecting a data logic stored in the memory cell based on a voltage difference between a first voltage of the first read bit line and a second voltage of the second read bit line.

    摘要翻译： 电路包括第一读取位线，第二读取位线和读出放大器。 第一和第二读取位线分别耦合存储器阵列的多个存储器单元和参考单元。 读出放大器被配置为接收第一读取位线作为第一输入，而第二读取位线作为第二输入。 当第一多个存储单元的存储单元被读取时，存储单元被读取激活，第一参考单元被配置为关闭，第二参考单元被配置为导通，并且读出放大器被配置为提供 基于第一读取位线的第一电压和第二读取位线的第二电压之间的电压差反映存储在存储器单元中的数据逻辑的输出。