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    Semi-synchronous receiver and apparatus for reading information
    2.
    发明授权
    Semi-synchronous receiver and apparatus for reading information 失效
    半同步接收机和读取信息的装置

    公开(公告)号：US07263049B2

    公开(公告)日：2007-08-28

    申请号：US10515465

    申请日：2003-04-30

    申请人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

    发明人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

    IPC分类号： G11B5/09

    CPC分类号： G11B20/10009 ,  G11B20/1403

    摘要： A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means (12) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter (13) converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator (14) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means (15) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector (16) for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means (40) are controlled by a preset value for keeping the ratio T/Ts constant.

    摘要翻译： 描述了用于从模拟信号（Sa）以数据速率1 / T递送数据序列（ak）的接收机，所述接收机包括：a）转换装置，用于通过对模拟信号进行采样来产生接收序列（rn） 信号（Sa），采样率为1 / Ts，由此接收序列（rn）的采样率1 / Ts可由预设值（Pv）控制; b）用于通过处理接收到的序列（rn）来传送经处理的序列（yn）的数字处理装置（12）; c）以数据速率1 / T将处理过的序列（yn）转换为等效处理序列（ye）的第一采样率转换器（13），由等效处理序列（ye）的数据速率由控制 信号（Sc）; d）用于从等效处理序列（ye）传送错误序列（ek）的误差发生器（14）; e）用于根据误差序列（ek）产生控制信号（Sc）的控制信号产生装置（15）; f）用于从等效处理序列（ye）导出数据序列（ak）的检测器（16），由此采样率1 / T和1 / Ts之间的比率基本上是恒定的。 包含采样率转换器的常规同步接收机的缺点在于在SRC的控制环路内进行数字处理。 数字处理造成的延迟有助于环路的整体延迟，这可能导致不稳定性，特别是当需要高带宽时。 因此，本发明的接收机在控制回路外进行数字处理。 为了保持以固定速率进行数字处理的优点，转换装置（40）由预设值控制，以保持比率T / Ts恒定。

    Semi-synchronous receiver and apparatus for reading information
    3.
    发明申请
    Semi-synchronous receiver and apparatus for reading information 失效
    半同步接收机和读取信息的装置

    公开(公告)号：US20060198467A1

    公开(公告)日：2006-09-07

    申请号：US10515465

    申请日：2003-04-30

    申请人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

    发明人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

    IPC分类号： H04L27/00

    CPC分类号： G11B20/10009 ,  G11B20/1403

    摘要： A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means (12) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter (13) for converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator (14) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means (15) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector (16) for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means (40) are controlled by a preset value for keeping the ratio T/Ts constant.

    摘要翻译： 描述了用于从模拟信号（Sa）以数据速率1 / T递送数据序列（ak）的接收机，所述接收机包括：a）转换装置，用于通过对模拟信号进行采样来产生接收序列（rn） 信号（Sa），采样率为1 / Ts，由此接收序列（rn）的采样率1 / Ts可由预设值（Pv）控制; b）用于通过处理接收到的序列（rn）来传送经处理的序列（yn）的数字处理装置（12）; c）用于以数据速率1 / T将处理过的序列（yn）转换为等效处理序列（ye）的第一采样率转换器（13），由此等效处理序列（ye）的数据速率可由 控制信号（Sc）; d）用于从等效处理序列（ye）传送错误序列（ek）的误差发生器（14）; e）用于根据误差序列（ek）产生控制信号（Sc）的控制信号产生装置（15）; f）用于从等效处理序列（ye）导出数据序列（ak）的检测器（16），由此采样率1 / T和1 / Ts之间的比率基本上是恒定的。 包含采样率转换器的常规同步接收机的缺点在于在SRC的控制环路内进行数字处理。 数字处理造成的延迟有助于环路的整体延迟，这可能导致不稳定性，特别是当需要高带宽时。 因此，本发明的接收机在控制回路外进行数字处理。 为了保持以固定速率进行数字处理的优点，转换装置（40）由预设值控制，以保持比率T / Ts恒定。