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1.发明申请公开(公告)号：US20150288485A1
公开(公告)日：2015-10-08
申请号：US14744015
申请日：2015-06-18
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的40G / 100G通信的应用的等待时间。 调制器具有用于将比特流映射成符号的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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2.发明申请公开(公告)号：US20140233673A1
公开(公告)日：2014-08-21
申请号：US14180315
申请日：2014-02-13
IPC分类号： H04L1/00
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 400/1000 communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的400/1000通信的应用的等待时间。 调制器具有用于将比特流映射成符号的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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3.发明授权公开(公告)号：US09413493B2
公开(公告)日：2016-08-09
申请号：US14744015
申请日：2015-06-18
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一个方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的40G / 100G通信的应用的延迟。 调制器具有用于将比特流映射到符号中的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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4.发明授权公开(公告)号：US09083492B2
公开(公告)日：2015-07-14
申请号：US14180315
申请日：2014-02-13
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的40G / 100G通信的应用的等待时间。 调制器具有用于将比特流映射成符号的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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