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公开(公告)号：US20170093436A1
公开(公告)日：2017-03-30
申请号：US15378904
申请日：2016-12-14
CPC分类号： H03M13/2778 , H03M13/2707 , H03M13/271 , H03M13/2742 , H03M13/2757 , H03M13/2767 , H03M13/2782 , H03M13/6502 , H04L1/0071
摘要： Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
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2.发明申请公开(公告)号：US20160322989A1
公开(公告)日：2016-11-03
申请号：US15206011
申请日：2016-07-08
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一个方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的40G / 100G通信的应用的延迟。 调制器具有用于将比特流映射到符号中的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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公开(公告)号：US20150309558A1
公开(公告)日：2015-10-29
申请号：US14791100
申请日：2015-07-02
IPC分类号： G06F1/32
CPC分类号： G06F1/3281 , G06F1/3206 , G06F1/3215 , G06F1/3234 , G06F1/3278 , G06F1/3287 , G06F1/3293 , H04L12/12 , Y02D10/157 , Y02D10/171 , Y02D50/20 , Y02D50/40 , Y02D50/42
摘要： Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.
摘要翻译： 公开了与数据接口功耗控制相关的装置和技术。 在数据传输模块不用于传输数据的时候，数据传输模块的组件可以在其正常操作状态和降低的功率状态之间选择性地移动。 关于要移动到其降低功率状态的特定组件的决定可以基于组件的各自的定时特性和/或组件的各自的功率消耗特性。 在一些实施例中，当数据传输模块的正常操作要恢复时，可以执行动作以减少数据传输模块的加电时间。 在具有用于每个连接的相应数据传输模块的多连接接口的情况下，可以通过将数据传输模块的子集移动到降低的功率状态来部分地关闭接口。
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4.发明申请公开(公告)号：US20150288485A1
公开(公告)日：2015-10-08
申请号：US14744015
申请日：2015-06-18
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的40G / 100G通信的应用的等待时间。 调制器具有用于将比特流映射成符号的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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公开(公告)号：US09075607B2
公开(公告)日：2015-07-07
申请号：US13935092
申请日：2013-07-03
CPC分类号： G06F1/3281 , G06F1/3206 , G06F1/3215 , G06F1/3234 , G06F1/3278 , G06F1/3287 , G06F1/3293 , H04L12/12 , Y02D10/157 , Y02D10/171 , Y02D50/20 , Y02D50/40 , Y02D50/42
摘要： Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.
摘要翻译： 公开了与数据接口功耗控制相关的装置和技术。 在数据传输模块不用于传输数据的时候，数据传输模块的组件可以在其正常操作状态和降低的功率状态之间选择性地移动。 关于要移动到其降低功率状态的特定组件的决定可以基于组件的各自的定时特性和/或组件的各自的功率消耗特性。 在一些实施例中，当数据传输模块的正常操作要恢复时，可以执行动作以减少数据传输模块的加电时间。 在具有用于每个连接的相应数据传输模块的多连接接口的情况下，可以通过将数据传输模块的子集移动到降低的功率状态来部分地关闭接口。
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公开(公告)号：US20150074500A1
公开(公告)日：2015-03-12
申请号：US14540907
申请日：2014-11-13
CPC分类号： H03M13/2778 , H03M13/2707 , H03M13/271 , H03M13/2742 , H03M13/2757 , H03M13/2767 , H03M13/2782 , H03M13/6502 , H04L1/0071
摘要： Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
摘要翻译： 各个不同维度的多个数据置换操作被用于使用比在单个置换操作中直接实现整体置换时使用的每个置换中更小的数据块来提供整体有效的数据置换。 在一个置换操作中已被置换的数据被块交织，并且随后的置换操作中交错的数据被置换。 矩阵转置是可以在置换操作之间应用的块交织的一个示例。
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公开(公告)号：US20140181319A1
公开(公告)日：2014-06-26
申请号：US14135111
申请日：2013-12-19
发明人： Charles Chen , Ryan Patrick Donohue , Donggun Keung , Xi Chen , Xiaochong Cao , Zeineddine Chair
IPC分类号： H04L12/801
CPC分类号： H04L47/33 , G06F13/385 , H04L69/08 , H04L69/12 , H04L69/321
摘要： Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware.
摘要翻译： 公开了通信业务处理架构和方法。 通过将数据处理任务卸载到单独的硬件，可以缓解主要中央处理单元（CPU）的处理负载。
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公开(公告)号：US20140053039A1
公开(公告)日：2014-02-20
申请号：US14066332
申请日：2013-10-29
IPC分类号： H03M13/27
CPC分类号： H03M13/2778 , H03M13/2707 , H03M13/271 , H03M13/2742 , H03M13/2757 , H03M13/2767 , H03M13/2782 , H03M13/6502 , H04L1/0071
摘要： Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
摘要翻译： 各个不同维度的多个数据置换操作被用于使用比在单个置换操作中直接实现整体置换时使用的每个置换中更小的数据块来提供整体有效的数据置换。 在一个置换操作中已被置换的数据被块交织，并且随后的置换操作中交错的数据被置换。 矩阵转置是可以在置换操作之间应用的块交织的一个示例。
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公开(公告)号：US09397702B2
公开(公告)日：2016-07-19
申请号：US14266299
申请日：2014-04-30
CPC分类号： H03M13/2906 , H03M13/15 , H03M13/2707 , H03M13/2721 , H03M13/2918 , H03M13/2927 , H03M13/3746 , H03M13/616 , H04J3/1658 , H04J14/08 , H04L1/0042 , H04L1/0057
摘要： In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code. Thus, each row in [Bi−1TBi] and each column in [ B i B i + 1 T ] for example, is a valid codeword.
摘要翻译： 在楼梯前向纠错编码中，将数据符号流映射到二维符号块Bi，i的序列中的数据符号位置为正整数。 每个符号块具有数据符号位置和编码符号位置。 计算序列中的每个符号块Bi中的编码符号位置的编码符号。 计算编码符号，使得对于具有先前符号块Bi-1的符号块Bi和序列中的后续符号块Bi + 1，在前一个符号块Bi-1的一维处的符号位置处的符号， 与符号块Bi中的沿着另一维度的数据符号和编码符号连接，形成FEC分量码的码字，以及沿符号块Bi的一个维度的符号位置处的符号，与数据符号和 沿着后续符号块Bi + 1中的另一维度编码符号，形成FEC分量代码的码字。 因此，[Bi-1TBi]中的每一行和[B i B i + 1 T]中的每列都是有效的代码字。
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10.发明授权公开(公告)号：US09083492B2
公开(公告)日：2015-07-14
申请号：US14180315
申请日：2014-02-13
CPC分类号： H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
摘要： For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
摘要翻译： 对于一些应用，例如通过短距离链路的高速通信，现有调制器提供的复杂性和相关联的高延迟可能是不合适的。 根据一方面，本公开提供了一种调制器，其可以减少诸如通过铜缆或SMF的40G / 100G通信的应用的等待时间。 调制器具有用于将比特流映射成符号的符号映射器，以及包括内部编码器和外部编码器的多电平编码器，用于只对位流的一部分进行编码。 在一些实现中，多电平编码器被配置为使得内编码器的信息块尺寸小并且匹配外编码器的场尺寸。 因此，可以省略用于适应较大块大小的组件。 效果是可以减少复杂性和延迟。 根据另一方面，本公开提供了一种与调制器互补的解调器。
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