公开(公告)号：US20180097669A1

公开(公告)日：2018-04-05

申请号：US15285272

申请日：2016-10-04

Applicant: Credo Technology Group Limited

Inventor： Runsheng He

IPC: H04L27/01 ,  H04B14/02

CPC classification number: H04L27/01 ,  H04B3/04 ,  H04B14/023 ,  H04B14/026

Abstract: Techniques for reducing the complexity and power requirements of precompensation units, as well as equalizers, devices, and systems employing such techniques. In an illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set; determining a distribution of threshold values for a precompensation unit corresponding to said channel response with said symbol set; deriving a reduced set of threshold values from said distribution; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the reduced set of threshold values. In a related illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set, the channel response and symbol set corresponding to an initial distribution of threshold values for a precompensation unit; deriving a filter that converts the channel response into a modified channel response, the modified channel response and symbol set corresponding to an improved distribution of threshold values in that the improved distribution includes fewer distinct threshold values or reduced spacing between at least some adjacent threshold values; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the threshold values in the improved distribution.

公开(公告)号：US09935800B1

公开(公告)日：2018-04-03

申请号：US15285272

申请日：2016-10-04

Applicant: Credo Technology Group Limited

Inventor： Runsheng He

IPC: H04L27/01 ,  H04B14/02

CPC classification number: H04L27/01 ,  H04B3/04 ,  H04B14/023 ,  H04B14/026

Abstract: Techniques for reducing the complexity and power requirements of precompensation units, as well as equalizers, devices, and systems employing such techniques. In an illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set; determining a distribution of threshold values for a precompensation unit corresponding to said channel response with said symbol set; deriving a reduced set of threshold values from said distribution; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the reduced set of threshold values. In a related illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set, the channel response and symbol set corresponding to an initial distribution of threshold values for a precompensation unit; deriving a filter that converts the channel response into a modified channel response, the modified channel response and symbol set corresponding to an improved distribution of threshold values in that the improved distribution includes fewer distinct threshold values or reduced spacing between at least some adjacent threshold values; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the threshold values in the improved distribution.

公开(公告)号：US09667407B1

公开(公告)日：2017-05-30

申请号：US15154567

申请日：2016-05-13

Applicant: Credo Technology Group Limited

Inventor： Xike Liu ,  Kei Peng ,  Chan Ho Yeung ,  YiFei Dai ,  Lawrence (Chi Fung) Cheng ,  Runsheng He

IPC: H04L7/00 ,  H04B10/61

CPC classification number: H04L7/0079 ,  H01F17/0006 ,  H03B5/1212 ,  H03B5/1228 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0812 ,  H03L7/091 ,  H03L7/099 ,  H04B10/6164 ,  H04B10/6165 ,  H04L7/0025 ,  H04L7/007 ,  H04L7/02

Abstract: A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive signal.