公开(公告)号：US08650447B1

公开(公告)日：2014-02-11

申请号：US13183147

申请日：2011-07-14

申请人： Curt Wortman ,  Keith Duwel ,  Huy Ngo

发明人： Curt Wortman ,  Keith Duwel ,  Huy Ngo

IPC分类号： G01R31/28 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/54 ,  G01R31/318516 ,  G11C29/04

摘要： In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.

摘要翻译： 根据本发明的实施例，错误注入的精确控制可以通过伴随数据路径的各个流水线级数据传输的同步误差信号来实现。 同步误差信号可用于触发给定协议逻辑块（即在数据路径的给定子组件中）的错误事件。 协议逻辑块是可配置的，以确定是否在断言错误信号时采取任何动作。 随着数据信号（及其伴随的同步误差信号）通过数据路径的流水线功能，可能会触发多个错误事件，从而创建复杂的错误条件。 此外，可以使用在正向和反向转换两者上具有可旁路块的环回路径来实现所创建的错误的确定性处理。 还公开了其它实施例，方面和特征。

公开(公告)号：US09736086B1

公开(公告)日：2017-08-15

申请号：US13098361

申请日：2011-04-29

申请人： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

发明人： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC分类号： H04L12/861

CPC分类号： H04L49/90 ,  H04L47/6245

摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

公开(公告)号：US08949493B1

公开(公告)日：2015-02-03

申请号：US12847761

申请日：2010-07-30

申请人： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

发明人： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F5/00 ,  G06F13/12 ,  G06M3/00 ,  G11C19/00 ,  G01R31/28 ,  G06F17/50 ,  G06F1/02 ,  G06F7/58 ,  H04L9/00

CPC分类号： H04L25/03866 ,  G06F3/00 ,  G06F5/00 ,  G06F7/58 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/4221 ,  G06F13/4282 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/285 ,  H04L9/00

摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

摘要翻译： 公开了与可配置加扰电路相关的各种结构和方法。 实施例可以被配置为支持多个协议中的一个。 一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。 一些实施例可配置为选择加扰器类型。 一些实施例可配置为适应多个协议特定的加扰多项式之一。 一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。 在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

公开(公告)号：US07095340B2

公开(公告)日：2006-08-22

申请号：US11087217

申请日：2005-03-22

申请人： Vinson Chan ,  Chong Lee ,  Huy Ngo

发明人： Vinson Chan ,  Chong Lee ,  Huy Ngo

IPC分类号： H03M7/00

CPC分类号： H03M5/145

摘要： Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

摘要翻译： 提供了用于检测数据流中类似的数据位的过量运行的电路。 数据流通常作为在串行时钟域中工作的串行数据来接收。 与较快的串行时钟域相反，运行长度检测电路在较慢的并行时钟域中运行时检查运行长度违例的接收数据。 在并行域中操作游程长度检测电路的优点是与在串行域中运行的游程长度检测器相比，可以在接收的数据中搜索更长的游程长度违例。 电路提供的另一个优点是可以异步地将运行长度违规信号提供给利用电路。 这使得尽管时钟域（即，检测电路的时钟域和利用电路的时钟域）有差异，但利用率电路可以快速地捕捉信号。

公开(公告)号：US20050162289A1

公开(公告)日：2005-07-28

申请号：US11087217

申请日：2005-03-22

申请人： Vinson Chan ,  Chong Lee ,  Huy Ngo

发明人： Vinson Chan ,  Chong Lee ,  Huy Ngo

IPC分类号： H03M5/14 ,  H03M7/00 ,  H03M7/46

CPC分类号： H03M5/145

摘要： Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. The circuitry of this of this invention checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage of the invention is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

摘要翻译： 提供了用于检测数据流中类似的数据位的过量运行的电路。 数据流通常作为在串行时钟域中工作的串行数据来接收。 与较快的串行时钟域相反，本发明的电路在较慢的并行时钟域中操作时检查所接收的数据的长度违反。 在并行域中操作游程长度检测电路的优点是与在串行域中运行的游程长度检测器相比，可以在接收的数据中搜索更长的游程长度违例。 本发明的另一个优点是可以异步地将游程长度违规信号提供给利用电路。 这使得尽管时钟域（即，检测电路的时钟域和利用电路的时钟域）有差异，但利用率电路可以快速地捕捉信号。

公开(公告)号：US06888480B1

公开(公告)日：2005-05-03

申请号：US10652907

申请日：2003-08-28

申请人： Vinson Chan ,  Chong Lee ,  Huy Ngo

发明人： Vinson Chan ,  Chong Lee ,  Huy Ngo

IPC分类号： H03M5/14 ,  H03M7/00

CPC分类号： H03M5/145

摘要： Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

摘要翻译： 提供了用于检测数据流中类似的数据位的过量运行的电路。 数据流通常作为在串行时钟域中工作的串行数据来接收。 与较快的串行时钟域相反，运行长度检测电路在较慢的并行时钟域中运行时检查运行长度违例的接收数据。 在并行域中操作游程长度检测电路的优点是与在串行域中运行的游程长度检测器相比，可以在接收的数据中搜索更长的游程长度违例。 电路提供的另一个优点是可以异步地将运行长度违规信号提供给利用电路。 这使得尽管时钟域（即，检测电路的时钟域和利用电路的时钟域）有差异，但利用率电路可以快速地捕捉信号。