公开(公告)号：US06985229B2

公开(公告)日：2006-01-10

申请号：US10158775

申请日：2002-05-30

申请人： Cynthia C. Lee ,  Stephen Arlon Meisner ,  Thomas Michael Wolf ,  Alberto Santoni ,  John Martin McIntosh

发明人： Cynthia C. Lee ,  Stephen Arlon Meisner ,  Thomas Michael Wolf ,  Alberto Santoni ,  John Martin McIntosh

IPC分类号： G01B11/00 ,  G01R31/26 ,  H01L21/66

CPC分类号： G03F7/70633 ,  G01B11/272

摘要： A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.

公开(公告)号：US07160799B2

公开(公告)日：2007-01-09

申请号：US10603041

申请日：2003-06-24

申请人： Steven Alan Lytle ,  Thomas Michael Wolf ,  Allen Yen

发明人： Steven Alan Lytle ,  Thomas Michael Wolf ,  Allen Yen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

摘要翻译： 本发明包括一种用于制造集成电路的方法，包括在导电材料上提供包括电介质层的衬底，在电介质层上沉积硬掩模，在硬掩模上施加第一光致抗蚀剂并对光栅定义沟槽，蚀刻硬掩模并部分地 蚀刻电介质以形成具有底部的沟槽，剥离光致抗蚀剂，施加第二光致抗蚀剂并且在沟槽之间照明定义狭缝，从沟槽的底部选择性地蚀刻电介质到下面的导电材料。 硬掩模和第二光致抗蚀剂均用作掩模。 之后，形成与底层金属的连接，由此形成集成电路。

公开(公告)号：US5780316A

公开(公告)日：1998-07-14

申请号：US879109

申请日：1997-06-19

申请人： Hongzong Chew ,  John David Cuthbert ,  Hamlet Herring ,  John Louis Ryan ,  Robert Ching-I Sun ,  Thomas Michael Wolf ,  Daniel Mark Wroge

发明人： Hongzong Chew ,  John David Cuthbert ,  Hamlet Herring ,  John Louis Ryan ,  Robert Ching-I Sun ,  Thomas Michael Wolf ,  Daniel Mark Wroge

IPC分类号： H01L21/82 ,  G03F7/20 ,  H01L23/544 ,  H01L21/00

CPC分类号： G03F7/70625 ,  G03F7/70658 ,  H01L22/34

摘要： Linewidth control features having integral transistors are disclosed. Optical and electrical measurements of the linewidth control feature and its associated transistor may be correlated thereby providing a method of improving production processes.

摘要翻译： 公开了具有整体晶体管的线宽控制特征。 可以将线宽控制特征及其相关联的晶体管的光学和电学测量相关联，从而提供改进生产工艺的方法。

公开(公告)号：US06559062B1

公开(公告)日：2003-05-06

申请号：US09713504

申请日：2000-11-15

申请人： Stephen Ward Downey ,  Allen Yen ,  Thomas Michael Wolf ,  Paul B. Murphey

发明人： Stephen Ward Downey ,  Allen Yen ,  Thomas Michael Wolf ,  Paul B. Murphey

IPC分类号： H01L21461

CPC分类号： H01L21/31116 ,  H01L21/32136

摘要： A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.

摘要翻译： 一种在半导体器件（82）中使用厚度（T）不大于0.66微米的光致抗蚀剂层（20）形成金属互连（102）的工艺（100），而不在侧面（30）中形成缺口 互连。 用于去除金属层（16）的部分以形成互连的反应离子蚀刻工艺（118）包括突发蚀刻步骤（108），其中递送钝化气体的第一高流速（48），随后是主体 金属蚀刻步骤（110），其中钝化气体的流速降低到第二较低值。