公开(公告)号：US08890600B1

公开(公告)日：2014-11-18

申请号：US13893201

申请日：2013-05-13

Applicant: Cypress Semiconductor Corporation

Inventor： Timothy J. Williams ,  Harold Kutz ,  David G. Wright ,  Eashwar Thiagarajan ,  Warren S. Snyder ,  Mark E. Hastings

IPC: H03L5/00

CPC classification number: G06F13/4022 ,  H03K19/1732

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.

Abstract translation: 一种可编程器件，具有与模拟总线耦合的模拟部件和与数字总线耦合的数字部件以及一组IO焊盘，每组IO能够耦合到模拟总线的一个部分的总线上 关于至少一个数字总线，并且其中模拟总线能够用于将一对IO焊盘彼此连接。

公开(公告)号：US09143134B1

公开(公告)日：2015-09-22

申请号：US13916386

申请日：2013-06-12

Applicant: Cypress Semiconductor Corporation

Inventor： Harold M. Kutz ,  Timothy J. Williams ,  Bert S. Sullam ,  Warren S. Snyder ,  James H. Shutt ,  Bruce E. Byrkett ,  Monte Mar ,  Eashwar Thiagarajan ,  Nathan Kohagen ,  David G. Wright ,  Mark E. Hastings ,  Dennis Raymond Seguine

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/173

CPC classification number: G01R31/3177 ,  G01R31/31721 ,  G06F13/28 ,  H03K19/173

Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.

Abstract translation: 描述了一种系统和装置，用于通过改进和高度可配置的路由，控制元件和信号处理能力在混合信号阵列中提供更大的灵活性和性能。

公开(公告)号：US09720865B1

公开(公告)日：2017-08-01

申请号：US14540238

申请日：2014-11-13

Applicant: Cypress Semiconductor Corporation

Inventor： Timothy J. Williams ,  David G. Wright ,  Harold Kutz ,  Eashwar Thiagarajan ,  Warren S. Snyder ,  Mark E Hastings

IPC: H03L5/00 ,  H01L25/00 ,  G06F13/40

CPC classification number: G06F13/4022 ,  H03K19/1732

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

公开(公告)号：US20130336081A1

公开(公告)日：2013-12-19

申请号：US13915464

申请日：2013-06-11

Applicant: Cypress Semiconductor Corporation

Inventor： Michael Sheets ,  Timothy J. Williams

IPC: G11C5/14

CPC classification number: G11C5/14 ,  H03K19/17764

Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.

Abstract translation: 本发明的实施例涉及一种状态监视存储元件。 状态监视存储器元件可以具有比IC上的其它常规存储器元件保持逻辑状态更低的能力。 因此，如果在测试期间状态监视存储器元件失败或失去状态，则可能是IC的状态保持可能存在危险的良好指示，可能需要IC复位。 状态监视存储元件可以通过在二极管和/或晶体管上降低对状态监视存储元件的输入电压供应来实现。 可以使用一个或多个电流源来压力状态监视存储元件。 可以使用逻辑分析器来分析状态监视存储器元件的完整性，并且响应于检测状态监视存储器元件中的故障而触发IC中的适当动作，例如复位，停止，移除电力，中断。 多个状态监视存储器元件可以分布在IC上的不同位置以获得更好的覆盖。