公开(公告)号：US20060051961A1

公开(公告)日：2006-03-09

申请号：US10935497

申请日：2004-09-07

申请人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

发明人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 退火步骤。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US20070123042A1

公开(公告)日：2007-05-31

申请号：US11164511

申请日：2005-11-28

申请人： Kern Rim ,  John Ellis-Monaghan ,  Brian Greene ,  William Henson ,  Robert Purtell ,  Clement Wann ,  Horatio Wildman

发明人： Kern Rim ,  John Ellis-Monaghan ,  Brian Greene ,  William Henson ,  Robert Purtell ,  Clement Wann ,  Horatio Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84

摘要： Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different suicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second suicides or germanides are performed sequentially or in a single step.

摘要翻译： 提供了制造半导体结构的方法，其包括位于半导体结构的不同区域中的异质自杀或锗化物。 异质自杀或锗化物形成在半导体层，导电层或两者上。 根据本发明，本发明的方法利用不同金属的顺序沉积和图案化的组合以在半导体芯片的不同区域中形成不同的自杀或锗化物。 该方法包括提供具有至少第一区域和第二区域的含Si或Ge层; 在所述第一或第二区域之一上形成第一硅化物或锗化物; 并且在不包括第一硅化物或锗化锗的另一区域上形成与第一硅化物或锗化物在组成上不同的第二硅化物或锗化物，其中形成第一和第二硅化物或锗化物的步骤依次进行或单步进行。

公开(公告)号：US20070210448A1

公开(公告)日：2007-09-13

申请号：US11308186

申请日：2006-03-10

申请人： Keith Wong ,  Yun-Yu Wang ,  Horatio Wildman ,  Christopher Parks ,  Chih-Chao Yang

发明人： Keith Wong ,  Yun-Yu Wang ,  Horatio Wildman ,  Christopher Parks ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the oxygen-getter layer and the metal-containing conductive material form MOL metallurgy where the Co-containing liner replaces a traditional TiN liner. By “Co-containing” is meant that the liner includes elemental Co alone or elemental Co and at least one of P or B. In order to provide better step coverage of the inventive Co-containing liner within a high aspect ratio contact opening, the Co-containing liner is formed via an electroless deposition process.

摘要翻译： 提供了包括设置在吸氧剂层和含金属的导电材料之间的含Co衬里的半导体结构。 含Co的内衬，吸氧剂层和含金属的导电材料形成MOL冶金，其中含Co衬垫代替了传统的TiN衬里。 “含Co”是指衬垫包括元素Co单体或元素Co以及P或B中的至少一种。为了在高纵横比接触开口内提供本发明的含Co衬垫的更好的台阶覆盖， 通过无电镀沉积工艺形成含钴内衬。

公开(公告)号：US20070222470A1

公开(公告)日：2007-09-27

申请号：US11308407

申请日：2006-03-22

申请人： Oliver Patterson ,  Horatio Wildman

发明人： Oliver Patterson ,  Horatio Wildman

IPC分类号： G01R31/26

CPC分类号： G01R31/311 ,  G01R31/2632

摘要： Structure and methods of determining the complete location of a buried short using voltage contrast inspection are disclosed. In one embodiment, a method includes providing a test structure having a PN junction thereunder; and using the PN junction to determine the location of the buried short using voltage contrast (VC) inspection. A test structure may include a plurality of test elements each having a PN junction thereunder, wherein a location of the buried short within the test structure can be determined using the PN junction and the VC inspection. The PN junction forces a change in illumination brightness of a test element including the buried short, thus allowing determination of the complete location of a buried short.

摘要翻译： 公开了使用电压对比度检查来确定埋入短路的完整位置的结构和方法。 在一个实施例中，一种方法包括提供其下具有PN结的测试结构; 并使用PN结确定使用电压对比（VC）检测的埋入短路的位置。 测试结构可以包括多个测试元件，每个测试元件具有下面的PN结，其中可以使用PN结和VC检查来确定测试结构内的埋入短路的位置。 PN接头强制包括埋入短路的测试元件的照明亮度变化，从而允许确定埋入短路的完整位置。

公开(公告)号：US20050221612A1

公开(公告)日：2005-10-06

申请号：US10708978

申请日：2004-04-05

申请人： Laura Brown ,  Fen Jamin ,  Kin-Sang Lam ,  Ying Li ,  Yun Wang ,  Horatio Wildman ,  Kwong Wong

发明人： Laura Brown ,  Fen Jamin ,  Kin-Sang Lam ,  Ying Li ,  Yun Wang ,  Horatio Wildman ,  Kwong Wong

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

摘要： The present invention is directed to a low thermal budget MOL liner to be used in the fabrication of a semiconductor device. The low thermal budget MOL liner of the present invention, which is formed by treating a titanium-deposited layer with an in-situ plasma nitridization step, results in a significantly improved high performance device as the need for the higher thermal annealing process presently used in the making of such devices can be avoided. The present invention is further directed to a method of making the resulting semiconductor device, as well as the semi-conductor device itself.

摘要翻译： 本发明涉及一种用于制造半导体器件的低热量预算MOL衬垫。 通过用原位等离子体氮化步骤处理钛沉积层形成的本发明的低热量预算MOL衬垫导致了显着改进的高性能器件，因为目前使用的较高热退火工艺 可以避免这种装置的制造。 本发明还涉及制造所得半导体器件以及半导体器件本身的方法。