公开(公告)号：US20130072092A1

公开(公告)日：2013-03-21

申请号：US13605363

申请日：2012-09-06

Applicant: Michael F. Lofaro ,  Mahadevaiyer Krishnan ,  Michael A. Cobb ,  Dennis G. Manzer

Inventor： Michael F. Lofaro ,  Mahadevaiyer Krishnan ,  Michael A. Cobb ,  Dennis G. Manzer

IPC: B24B1/00

CPC classification number: B24B37/30 ,  B24B27/0069 ,  B24B27/0076 ,  B24B37/105 ,  B24B37/245 ,  B24B37/345 ,  B24B41/047

Abstract: An apparatus for chemical mechanical planarization includes a spindle assembly structure and at least one substrate carrier, which make a linear lateral movement relative to each other while abrasive surfaces of a plurality of cylindrical spindles in the spindle assembly structure contact, and rotate against, at least one substrate mounted on the at least one substrate carrier. The direction of the linear lateral movement is within the plane that tangentially contacts the plurality of cylindrical spindles, and can be orthogonal to the axes of rotation of the plurality of cylindrical spindles.

公开(公告)号：US20120329200A1

公开(公告)日：2012-12-27

申请号：US13165339

申请日：2011-06-21

Applicant: Mahadevaiyer Krishnan ,  Jun Liu ,  Satyavolu S. Papa Rao ,  George G. Totir

Inventor： Mahadevaiyer Krishnan ,  Jun Liu ,  Satyavolu S. Papa Rao ,  George G. Totir

IPC: H01L31/18 ,  C09K13/02 ,  C09K13/00 ,  B82Y30/00

CPC classification number: H01L31/03845 ,  B82Y30/00 ,  C09K13/02 ,  H01L31/02363 ,  H01L31/1804 ,  H01L31/186 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.

Abstract translation: 提供了一种纹理化晶体硅衬底表面的方法。 该方法包括将晶体硅衬底浸入碱性蚀刻剂水溶液中，以形成在晶体硅衬底上（111）面暴露的金字塔形纹理表面。 用于本公开方法的碱性蚀刻剂水溶液包括碱性组分和纳米颗粒淤浆组分。 具体地说，本公开的碱性蚀刻剂水溶液包含0.5重量％至5重量％的碱性组分和0.1重量％至5重量％的基于干基的纳米颗粒浆料。

公开(公告)号：US20090309228A1

公开(公告)日：2009-12-17

申请号：US12539660

申请日：2009-08-12

Applicant: Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

Inventor： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

IPC: H01L23/532 ,  H01L21/306

CPC classification number: H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract translation: 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US20060134911A1

公开(公告)日：2006-06-22

申请号：US10905230

申请日：2004-12-22

Applicant: Darryl Restaino ,  Donald Canaperi ,  Judith Rubino ,  Sean Smith ,  Richard Henry ,  James Fluegel ,  Mahadevaiyer Krishnan

Inventor： Darryl Restaino ,  Donald Canaperi ,  Judith Rubino ,  Sean Smith ,  Richard Henry ,  James Fluegel ,  Mahadevaiyer Krishnan

IPC: H01L21/44

CPC classification number: H01L21/288 ,  C23C18/1241 ,  C23C18/1607 ,  C23C18/1608 ,  C23C18/1844 ,  C23C18/50 ,  H01L21/76849 ,  H01L21/76874 ,  H05K3/244 ,  H05K2203/0716 ,  H05K2203/072

Abstract: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.

Abstract translation: 一种以可再生的方式对铜上的CoWP合金进行无电镀的方法，该方法对于可制造的工艺是有效的。 在该方法中，通过乙酸钯，乙酸和氯化物的水性接种溶液将铜（Pd）种子层沉积在铜上。 此后，应用络合溶液以除去吸附在除铜之外的表面上的任何Pd离子。 最后，将铜（Co），钨（W）和磷（P）的电镀溶液施加到铜上，以便在Pd种子和铜上沉积CoWP层。

公开(公告)号：US07045453B2

公开(公告)日：2006-05-16

申请号：US11104764

申请日：2005-04-12

Applicant: Donald F. Canaperi ,  Timothy J. Dalton ,  Stephen M. Gates ,  Mahadevaiyer Krishnan ,  Satya V. Nitta ,  Sampath Purushothaman ,  Sean P. E. Smith

Inventor： Donald F. Canaperi ,  Timothy J. Dalton ,  Stephen M. Gates ,  Mahadevaiyer Krishnan ,  Satya V. Nitta ,  Sampath Purushothaman ,  Sean P. E. Smith

IPC: H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Abstract translation: 一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能的互连。 布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中布置非常低的k和较不稳定的间隙填充电介质，使得该结构将耐用层与强度非常相似 低k电介质用于互连电气性能。

公开(公告)号：US07023093B2

公开(公告)日：2006-04-04

申请号：US10280283

申请日：2002-10-24

Applicant: Donald F. Canaperi ,  Timothy J. Dalton ,  Stephen M. Gates ,  Mahadevaiyer Krishnan ,  Satya V. Nitta ,  Sampath Purushothaman ,  Sean P. E. Smith

Inventor： Donald F. Canaperi ,  Timothy J. Dalton ,  Stephen M. Gates ,  Mahadevaiyer Krishnan ,  Satya V. Nitta ,  Sampath Purushothaman ,  Sean P. E. Smith

IPC: H01L23/48

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Abstract translation: 一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。 布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中设置非常低的k和较不牢固的间隙填充电介质，使得该结构将耐用层与强度非常低 k电介质用于互连电性能。

公开(公告)号：US06348076B1

公开(公告)日：2002-02-19

申请号：US09472961

申请日：1999-12-28

Applicant: Donald F. Canaperi ,  William J. Cote ,  Paul Feeney ,  Mahadevaiyer Krishnan ,  Joyce C. Liu ,  Michael F. Lofaro ,  Philip Murphy ,  Eric Jeffrey White

Inventor： Donald F. Canaperi ,  William J. Cote ,  Paul Feeney ,  Mahadevaiyer Krishnan ,  Joyce C. Liu ,  Michael F. Lofaro ,  Philip Murphy ,  Eric Jeffrey White

IPC: C09G102

CPC classification number: C23F3/00 ,  C09G1/02 ,  H01L21/3212

Abstract: Slurry compositions comprising an oxidizing agent, copper corrosion inhibitor, abrasive particles; surface active agent and polyelectrolyte are useful for polishing or planarizing chip interconnect/wiring material such as Al, W and especially Cu.

Abstract translation: 包含氧化剂，铜缓蚀剂，磨料颗粒的浆料组合物; 表面活性剂和聚电解质可用于抛光或平面化芯片互连/布线材料如Al，W，特别是Cu。

公开(公告)号：US06190237B1

公开(公告)日：2001-02-20

申请号：US08965218

申请日：1997-11-06

Applicant: Cuc Kim Huynh ,  Mahadevaiyer Krishnan ,  Michael Joseph MacDonald ,  Mark Peter Murray

Inventor： Cuc Kim Huynh ,  Mahadevaiyer Krishnan ,  Michael Joseph MacDonald ,  Mark Peter Murray

IPC: B24B100

CPC classification number: H01L21/3212 ,  C09G1/02 ,  C09K3/1463

Abstract: A slurry containing abrasive particles and a pH buffering component comprising at least one acid or salt thereof and at least one base is especially useful for polishing surfaces, including those used in microelectronics.

Abstract translation: 含有研磨颗粒和包含至少一种酸或其盐和至少一种碱的pH缓冲组分的浆液特别适用于抛光表面，包括微电子学中使用的表面。

公开(公告)号：US4818286A

公开(公告)日：1989-04-04

申请号：US165663

申请日：1988-03-08

Applicant: Rangarajan Jagannathan ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

Inventor： Rangarajan Jagannathan ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

IPC: C23C18/40 ,  C23C18/38 ,  B05D3/10

CPC classification number: C23C18/40

Abstract: An electroless copper plating bath contains copper sulfate, EDTA, DMAB and triethanolamine and is adjusted to a pH in the range between approximately 8 and 9. The addition of cyanide ions alone or preferably with a sulfur compound such as thiodipropionic acid or a nitrogen compound such as 1,10 phenanthroline provided bright copper deposits. The use of an electroless plating bath operating at a low pH permits electroless plating of alkali sensitive substrates.

公开(公告)号：US08637405B2

公开(公告)日：2014-01-28

申请号：US13165339

申请日：2011-06-21

Applicant: Mahadevaiyer Krishnan ,  Jun Liu ,  Satyavolu S. Papa Rao ,  George G. Totir

Inventor： Mahadevaiyer Krishnan ,  Jun Liu ,  Satyavolu S. Papa Rao ,  George G. Totir

IPC: H01L31/18 ,  C09K13/02

CPC classification number: H01L31/03845 ,  B82Y30/00 ,  C09K13/02 ,  H01L31/02363 ,  H01L31/1804 ,  H01L31/186 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.