公开(公告)号：US20190181856A1

公开(公告)日：2019-06-13

申请号：US16278337

申请日：2019-02-18

Applicant: DENSO CORPORATION

Inventor： Yoshitaka KATO ,  Kenji KOMIYA ,  Yusuke SHINDO ,  Yoshinori HAYASHI ,  Kenichi WAKABAYASHI

IPC: H03K17/16 ,  H02M1/08 ,  H02M1/32 ,  H02M7/537

CPC classification number: H03K17/166 ,  H02M1/08 ,  H02M1/32 ,  H02M3/158 ,  H02M7/537 ,  H02M7/53875 ,  H02M2001/0009 ,  H02M2001/007 ,  H03K2217/0081

Abstract: A semiconductor device turns on and off a power switching device having a gate terminal and output terminals between which an output current is produced by a gate voltage applied to the gate terminal. The semiconductor device includes: an output current detector detecting a current value correlated with the output current; a voltage detector detecting a voltage across the output terminals of the power switching device; a clamp circuit clamping the gate voltage at a predetermined value; and a controller controlling the clamp circuit to adjust the gate voltage based on the voltage detected by the voltage detector. The controller controls the clamp circuit to set the gate voltage to be at a minimum voltage according to the detected voltage to cause the output current to be larger than a threshold current required for detecting the short circuit in the power switching device.

公开(公告)号：US20210098442A1

公开(公告)日：2021-04-01

申请号：US17034678

申请日：2020-09-28

Applicant: DENSO CORPORATION

Inventor： Satoru SUGITA ,  Kosuke YUZAWA ,  Susumu YAMADA ,  Kenji KOMIYA

IPC: H01L25/18 ,  H01L23/495 ,  H01L23/00 ,  H02M3/158

Abstract: A semiconductor device includes, a semiconductor element, a wiring member arranged to sandwich the semiconductor element, a sealing resin body. The semiconductor element has an SBD formed thereon with a base material of SiC which is a wide band gap semiconductor. The semiconductor element has two main electrodes on both surfaces. The wiring member includes (i) a heat sink electrically connected to a first main electrode and (ii) a heat sink and a terminal electrically connected to a second main electrode. The semiconductor device further includes an insulator. The insulator has a non-conducting element made of silicon. The insulator has joints on both of two surfaces for mechanical connection of the heat sinks.

公开(公告)号：US20170126210A1

公开(公告)日：2017-05-04

申请号：US15318390

申请日：2015-06-23

Applicant: DENSO CORPORATION

Inventor： Kenji KOMIYA

IPC: H03K3/012 ,  H02M1/08

CPC classification number: H03K3/012 ,  H02M1/08 ,  H03K17/08122 ,  H03K17/162

Abstract: A drive device includes a main power supply coupled to a driver circuit for controlling on and off of a switching element; a first capacitor coupled, in parallel with the driver circuit, to the main power supply and disposed with no element other than wiring interposed between the first capacitor and the driver circuit; and an impedance element coupled, in series with the first capacitor and the driver circuit, to the main power supply and disposed with no element other than wiring interposed between the impedance element and the first capacitor and between the impedance element and the driver circuit. Electrostatic capacitance C1 of the first capacitor satisfies the following relationship with respect to gate capacitance Cgs of the switching element and intermediate potential Vdr present between the driver circuit and the impedance element in a state of the first capacitor being fully charged: V th V dr - V th  C gs

公开(公告)号：US20210367048A1

公开(公告)日：2021-11-25

申请号：US17394278

申请日：2021-08-04

Applicant: DENSO CORPORATION

Inventor： Susumu YAMADA ,  Satoru SUGITA ,  Kenji KOMIYA

IPC: H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor chip, first and second conductive members disposed on opposite sides of the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a surface electrode and gate wirings. The semiconductor substrate has active regions formed with elements, and an inactive region not formed with an element. The inactive region includes an inter-inactive portion disposed between at least two active regions and an outer peripheral inactive portion disposed on an outer periphery of the at least two active regions. The surface electrode is disposed to continuously extend above the at least two active regions and the inter-inactive portion. The gate wirings are disposed above the inactive region, and include a first gate wiring disposed on an outer periphery of the surface electrode, and a second gate electrode disposed at a position facing the surface electrode.