公开(公告)号：US10854589B2

公开(公告)日：2020-12-01

申请号：US16507240

申请日：2019-07-10

Applicant: DENSO CORPORATION

Inventor： Satoru Sugita ,  Ryota Tanabe ,  Shunsuke Arai

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/367 ,  H01L23/473 ,  H01L29/417 ,  H02M7/537

Abstract: A semiconductor device includes a first semiconductor module and a second semiconductor module. The first semiconductor module configures an upper arm, and includes first semiconductor elements connected in parallel to each other, a sealing resin body, and a positive electrode terminal. The second semiconductor module configures a lower arm, and includes second semiconductor elements connected in parallel to each other, a sealing resin body, and a negative electrode terminal. The first and second semiconductor modules are aligned in an alignment direction. At least one of the first and second semiconductor modules has a relay terminal for electrically relaying electrodes on a low potential side of the first semiconductor elements and electrodes on a high potential side of the second semiconductor elements.

公开(公告)号：US20140105767A1

公开(公告)日：2014-04-17

申请号：US14052810

申请日：2013-10-14

Applicant: DENSO CORPORATION

Inventor： Akira IWABUCHI ,  Masao Yamada ,  Kenji Onoda ,  Satoru Sugita ,  Takayoshi Sakashita

IPC: H05K7/00

CPC classification number: H05K7/00 ,  H01L2224/48091 ,  H05K7/1432 ,  H01L2924/00014

Abstract: A power supply module configured to supply power to a load having a first connector terminal includes a body, an insulating member, and a second connector terminal. The body includes a frame for power supply. The insulating member seals the body such that the frame is exposed from the insulating member. The second connector terminal is configured to be fitted with the first connector terminal and is bonded to the frame.

Abstract translation: 被配置为向具有第一连接器端子的负载供电的电源模块包括主体，绝缘构件和第二连接器端子。 身体包括一个用于供电的框架。 绝缘构件密封体，使得框架从绝缘构件露出。 第二连接器端子被配置为与第一连接器端子配合并且接合到框架。

公开(公告)号：US11587921B2

公开(公告)日：2023-02-21

申请号：US17034678

申请日：2020-09-28

Applicant: DENSO CORPORATION

Inventor： Satoru Sugita ,  Kosuke Yuzawa ,  Susumu Yamada ,  Kenji Komiya

IPC: H01L25/18 ,  H01L23/00 ,  H02M3/158 ,  H01L23/495 ,  H01L23/373 ,  H02P27/06 ,  B60L50/51

Abstract: A semiconductor device includes, a semiconductor element, a wiring member arranged to sandwich the semiconductor element, a sealing resin body. The semiconductor element has an SBD formed thereon with a base material of SiC which is a wide band gap semiconductor. The semiconductor element has two main electrodes on both surfaces. The wiring member includes (i) a heat sink electrically connected to a first main electrode and (ii) a heat sink and a terminal electrically connected to a second main electrode. The semiconductor device further includes an insulator. The insulator has a non-conducting element made of silicon. The insulator has joints on both of two surfaces for mechanical connection of the heat sinks.

公开(公告)号：US11749731B2

公开(公告)日：2023-09-05

申请号：US17394278

申请日：2021-08-04

Applicant: DENSO CORPORATION

Inventor： Susumu Yamada ,  Satoru Sugita ,  Kenji Komiya

IPC: H01L29/417 ,  H01L29/423 ,  H01L23/34 ,  H01L23/495 ,  H01L23/00 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L29/4238 ,  H01L23/34 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/33 ,  H01L24/73 ,  H01L29/0696 ,  H01L29/41741 ,  H01L2224/33181 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/10272

Abstract: A semiconductor device includes a semiconductor chip, first and second conductive members disposed on opposite sides of the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a surface electrode and gate wirings. The semiconductor substrate has active regions formed with elements, and an inactive region not formed with an element. The inactive region includes an inter-inactive portion disposed between at least two active regions and an outer peripheral inactive portion disposed on an outer periphery of the at least two active regions. The surface electrode is disposed to continuously extend above the at least two active regions and the inter-inactive portion. The gate wirings are disposed above the inactive region, and include a first gate wiring disposed on an outer periphery of the surface electrode, and a second gate electrode disposed at a position facing the surface electrode.