公开(公告)号：US20190008042A1

公开(公告)日：2019-01-03

申请号：US16065140

申请日：2016-11-30

Applicant: DENSO CORPORATION

Inventor： Kiyokazu AKIYAMA ,  Yasunari YANAGIBA

IPC: H05K1/03 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H01L23/66

CPC classification number: H05K1/03 ,  H01L23/66 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K3/46 ,  H05K2201/096 ,  H05K2201/09618

Abstract: A first land and a first ground pattern generate a first parasitic capacitance CLAND by capacitive coupling with a first insulating layer interposed therebetween. Then, the first parasitic capacitance CLAND is defined as a predetermined capacitance that suppresses an impedance of a via part from changing due to a change in an inductance component of the via part with respect to a first transmission line. As a result, it is possible to match the impedance of the via part with a impedance of the first transmission line by adjusting the first parasitic capacitance CLAND caused by the first land and the first ground pattern. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate from deteriorating without requiring the disposition of cavities such as through holes in the multilayer substrate.