公开(公告)号：US07118962B2

公开(公告)日：2006-10-10

申请号：US10982005

申请日：2004-11-04

申请人： Da-soon Lee

发明人： Da-soon Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same.The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

摘要翻译： 本发明公开了一种能够提高数据存储容量而不增加装置的表面积的非易失性存储装置及其制造方法。 非易失性存储器件包括：形成在半导体衬底的有源区上的堆叠型结构的栅极; 在堆叠型结构的栅极的两侧形成在基板中的源极/漏极; 形成在基板上形成源极/漏极并覆盖堆叠型结构的栅极的层间绝缘膜; 通过层间绝缘膜连接到源极/漏极的触点; 多个导电图案形成在与接触不相邻的区域的层间绝缘膜中; 以及形成在导电图案上的电极焊盘。

公开(公告)号：US20130075857A1

公开(公告)日：2013-03-28

申请号：US13465593

申请日：2012-05-07

申请人： Hyung-suk CHOI ,  Hyun-tae Jung ,  Eung-ryul Park ,  Da-soon Lee

发明人： Hyung-suk CHOI ,  Hyun-tae Jung ,  Eung-ryul Park ,  Da-soon Lee

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/761 ,  H01L21/76224

摘要： An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

公开(公告)号：US09105684B2

公开(公告)日：2015-08-11

申请号：US13465593

申请日：2012-05-07

申请人： Hyung-suk Choi ,  Hyun-tae Jung ,  Eung-ryul Park ,  Da-soon Lee

发明人： Hyung-suk Choi ,  Hyun-tae Jung ,  Eung-ryul Park ,  Da-soon Lee

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L21/761

CPC分类号： H01L29/0649 ,  H01L21/761 ,  H01L21/76224

摘要： An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

摘要翻译： 提供半导体的隔离结构，具有该隔离结构的半导体器件以及用于制造隔离结构的方法。 半导体器件的隔离结构可以包括形成在衬底中的沟槽，形成在沟槽的底表面和内侧壁上的氧化物层，形成在氧化物层上以填充沟槽内部的一部分的填充物，以及 将沟槽的填料的上部填充到沟槽的上表面上方的高度的第四氧化物层，在内侧壁和氧化物层之间的边界区域上形成底切结构。

公开(公告)号：US20050020012A1

公开(公告)日：2005-01-27

申请号：US10827456

申请日：2004-04-19

申请人： Da-soon Lee

发明人： Da-soon Lee

IPC分类号： H01L21/336 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： The present invention discloses a method for manufacturing a nonvolatile memory transistor capable of minimizing the area when adapted to the technology of sub-micron. The method comprises the steps of forming a trench of a predetermined shape on a silicon substrate; forming a N+ type doped region; etching the silicon substrate; forming ion implanted regions on the sides of the trench by conducting an inclined ion implantation for threshold voltage Vt control ion implantation of a select transistor; forming a poly-1 layer by depositing an oxide film and then depositing poly-1 serving as a gate node of the select transistor; after the formation of the poly-1 layer, conducting an etchback to the poly-1 layer; forming N+ ion implanted regions by conducting a N-type ion implantation in order to form a N+ source junction of a cell transistor; forming a channel of an EEPROM by additionally etching the silicon substrate; forming cell threshold voltage ion implanted regions by conducting an ion implantation in order to control the threshold voltage Vt of the channel of the cell; after the cell threshold voltage ion implantation, forming a cell gate oxide film by conducting the gate oxidation of the cell; forming a poly-2 layer by depositing poly-2 and then conducting an etchback; forming cell N-type drain junction regions by conducting an ion implantation in order to form a cell N-type drain junction; etching the poly-2 layer into a predetermined shape in order to form a control gate of the cell overlapped with the poly-2; forming a ply-3 layer by depositing an oxide film, depositing poly-3 and conducting an etchback; and filling an oxide film so as to be penetrated into the poly-3 layer, the oxide film, the poly-2 layer, the cell gate oxide film, the poly-1 layer and the oxide film under the poly-1 layer.

摘要翻译： 本发明公开了一种制造非易失性存储晶体管的方法，该方法能适应亚微米技术的最小化。 该方法包括以下步骤：在硅衬底上形成预定形状的沟槽; 形成N +型掺杂区域; 蚀刻硅衬底; 通过对选择晶体管的阈值电压Vt控制离子注入进行倾斜离子注入，在沟槽的侧面上形成离子注入区域; 通过沉积氧化膜形成多晶硅层，然后沉积用作选择晶体管的栅极节点的多晶硅1; 在形成多晶硅层之后，对多晶硅层进行回蚀; 通过进行N型离子注入形成N +离子注入区，以形成单元晶体管的N +源极结; 通过另外蚀刻硅衬底形成EEPROM的沟道; 通过进行离子注入来形成电池阈值电压离子注入区域，以便控制电池沟道的阈值电压Vt; 在电池阈值电压离子注入之后，通过进行电池的栅极氧化形成电池栅极氧化膜; 通过沉积poly-2然后进行回蚀而形成聚-2层; 通过进行离子注入来形成电池N型漏极结区域，以形成电池N型漏极结; 将聚-2层蚀刻成预定的形状，以便形成与聚合物2重叠的电池的控制栅极; 通过沉积氧化膜形成层3层，沉积多晶硅3并进行回蚀; 并填充氧化膜，以便渗透到poly-3层，多晶硅层，多晶硅层，多晶硅层，多晶硅层，多晶硅层1和多晶硅层1的氧化物膜。

公开(公告)号：US20050093056A1

公开(公告)日：2005-05-05

申请号：US10982005

申请日：2004-11-04

申请人： Da-soon Lee

发明人： Da-soon Lee

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

摘要翻译： 本发明公开了一种能够提高数据存储容量而不增加装置的表面积的非易失性存储装置及其制造方法。 非易失性存储器件包括：形成在半导体衬底的有源区上的堆叠型结构的栅极; 在堆叠型结构的栅极的两侧形成在基板中的源极/漏极; 形成在基板上形成源极/漏极并覆盖堆叠型结构的栅极的层间绝缘膜; 通过层间绝缘膜连接到源极/漏极的触点; 多个导电图案形成在与接触不相邻的区域的层间绝缘膜中; 以及形成在导电图案上的电极焊盘。

公开(公告)号：US06846713B1

公开(公告)日：2005-01-25

申请号：US10827456

申请日：2004-04-19

申请人： Da-soon Lee

发明人： Da-soon Lee

IPC分类号： H01L21/336 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： The present invention discloses a method for manufacturing a nonvolatile memory transistor capable of minimizing the area when adapted to the technology of sub-micron. The method comprises the steps of forming a trench of a predetermined shape on a silicon substrate; forming a N+ type doped region; etching the silicon substrate; forming ion implanted regions on the sides of the trench by conducting an inclined ion implantation for threshold voltage Vt control ion implantation of a select transistor; forming a poly-1 layer by depositing an oxide film and then depositing poly-1 serving as a gate node of the select transistor, after the formation of the poly-1 layer, conducting an etchback to the poly-1 layer, forming N+ ion implanted regions by conducting a N-type ion implantation in order to form a N+ source junction of a cell transistor; forming a channel of an EEPROM by additionally etching the silicon substrate; forming cell threshold voltage ion implanted regions by conducting an ion implantation in order to control the threshold voltage Vt of the channel of the cell; after the cell threshold voltage ion implantation, forming a cell gate oxide film by conducting the gate oxidation of the cell; forming a poly-2 layer by depositing poly-2 and then conducting an etchback; forming cell N-type drain junction regions by conducting an ion implantation in order to form a cell N-type drain junction; etching the poly-2 layer into a predetermined shape in order to form a control gate of the cell overlapped with the poly-2; forming a ply-3 layer by depositing an oxide film, depositing poly-3 and conducting an etchback; and filling an oxide film so as to be penetrated into the poly-3 layer, the oxide film, the poly-2 layer, the cell gate oxide film, the poly-1 layer and the oxide film under the poly-1 layer.

摘要翻译： 本发明公开了一种制造非易失性存储晶体管的方法，该方法能适应亚微米技术的最小化。 该方法包括以下步骤：在硅衬底上形成预定形状的沟槽; 形成N +型掺杂区域; 蚀刻硅衬底; 通过对选择晶体管的阈值电压Vt控制离子注入进行倾斜离子注入，在沟槽的侧面上形成离子注入区域; 通过沉积氧化膜形成多晶硅层，然后在形成多晶硅层之后沉积多晶硅1作为选择晶体管的栅极节点，对多晶硅层进行回蚀，形成N +离子注入 通过进行N型离子注入以形成单元晶体管的N +源极结; 通过另外蚀刻硅衬底形成EEPROM的沟道; 通过进行离子注入来形成电池阈值电压离子注入区域，以便控制电池沟道的阈值电压Vt; 在电池阈值电压离子注入之后，通过进行电池的栅极氧化形成电池栅极氧化膜; 通过沉积poly-2然后进行回蚀而形成聚-2层; 通过进行离子注入来形成电池N型漏极结区域，以形成电池N型漏极结; 将聚-2层蚀刻成预定的形状，以便形成与聚合物2重叠的电池的控制栅极; 通过沉积氧化膜形成层3层，沉积多晶硅3并进行回蚀; 并填充氧化膜，以便渗透到poly-3层，多晶硅层，多晶硅层，多晶硅层，多晶硅层，多晶硅层1和多晶硅层1的氧化物膜。