公开(公告)号：US20060018417A1

公开(公告)日：2006-01-26

申请号：US11185825

申请日：2005-07-21

申请人： Dae-Seung Jeong ,  Ki-Mio Ueda ,  Duck Chang ,  Hwa-Su Koh ,  Young-Gyu Kang ,  Shu-Jiang Wang ,  Soon-Bok Jang ,  Nyun-Tae Kim

发明人： Dae-Seung Jeong ,  Ki-Mio Ueda ,  Duck Chang ,  Hwa-Su Koh ,  Young-Gyu Kang ,  Shu-Jiang Wang ,  Soon-Bok Jang ,  Nyun-Tae Kim

IPC分类号： H03D3/22

CPC分类号： H03L7/091 ,  H04L7/033

摘要： The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

摘要翻译： 相位检测电路可以允许半导体电路的操作速度增加，而不管半导体电路内的组合逻辑电路是否以较低的操作速度操作。 相位检测电路可以调整输入数据信号的数据速率并选择性地启用参考信号和误差信号。 相位检测电路可以包括在时钟数据恢复电路内。

公开(公告)号：US20060013349A1

公开(公告)日：2006-01-19

申请号：US11179558

申请日：2005-07-13

申请人： Hwa Koh ,  Ki Ueda ,  Duck Chang ,  Nyun Kim ,  Dae Jeong

发明人： Hwa Koh ,  Ki Ueda ,  Duck Chang ,  Nyun Kim ,  Dae Jeong

IPC分类号： H03D3/24

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H04L7/0025 ,  H04L7/0337

摘要： A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.

公开(公告)号：US20060023779A1

公开(公告)日：2006-02-02

申请号：US11189879

申请日：2005-07-27

申请人： Myoung Kwak ,  Duck Chang ,  Ji Kim ,  Chi Kim ,  Hyun Kim ,  Jae Park ,  Jong Shin

发明人： Myoung Kwak ,  Duck Chang ,  Ji Kim ,  Chi Kim ,  Hyun Kim ,  Jae Park ,  Jong Shin

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： An equalizer may include an equalizer circuit and a controller. The equalizer circuit may generate an equalized signal based on a control code and input data. The controller may generate the control code based on a transition information signal having information on a number of data transitions in each clock period between multi-phase clocks.

摘要翻译： 均衡器可以包括均衡器电路和控制器。 均衡器电路可以基于控制代码和输入数据生成均衡信号。 控制器可以基于具有关于在多个时钟之间的每个时钟周期内的数据转换的数量的信息的转换信息信号来产生控制代码。