公开(公告)号：US07965536B2

公开(公告)日：2011-06-21

申请号：US12560206

申请日：2009-09-15

申请人： Daisuke Hashimoto ,  Daisaburo Takashima ,  Hidehiro Shiga

发明人： Daisuke Hashimoto ,  Daisaburo Takashima ,  Hidehiro Shiga

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.

摘要翻译： 根据本发明的一个方面，提供了一种铁电存储器件，它包括：一个单元单元，包括：具有第一源极，第一漏极和第一栅极的第一选择晶体管，第一源极和第一漏极之一 连接到位线; 以及具有多个第一存储单元的存储单元单元，每个第一存储单元包括第一铁电电容器和第一存储晶体管; 以及铁电存储器熔丝，包括：第二选择晶体管，具有连接到第二选择线的第二源极，第二漏极和第二栅极，所述第二源极和所述第二漏极中的一个连接到所述位线的一端; 以及具有多个第二存储单元的存储器熔丝单元，每个第二存储单元包括第二铁电电容器和第二存储晶体管。

公开(公告)号：US08059445B2

公开(公告)日：2011-11-15

申请号：US12563950

申请日：2009-09-21

申请人： Daisuke Hashimoto ,  Daisaburo Takashima ,  Hidehiro Shiga

发明人： Daisuke Hashimoto ,  Daisaburo Takashima ,  Hidehiro Shiga

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/406

摘要： A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.

摘要翻译： 根据本发明的实施例的铁电存储器包括：存储单元阵列，包括多个存储单元，并且具有多个字线，多个位线和多个板线，每个板线对应于该字中的至少两个 线路，被配置为对从所述存储器单元中选择的所选择的单元执行访问操作的访问控制电路;以及刷新控制电路，被配置为在所述访问操作的后台中执行刷新操作，所述更新单元是 从所述存储单元中选择所述刷新控制电路，所述刷新控制电路在连接到所选择的单元的板线和连接到所选择的单元的位线之间执行刷新操作，在所述访问操作之后处于相同的电位。

公开(公告)号：US08134349B2

公开(公告)日：2012-03-13

申请号：US12404438

申请日：2009-03-16

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G05F1/613

CPC分类号： G05F1/56

摘要： A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

摘要翻译： 电源电路具有恒压电路，第一MOS晶体管，第二MOS晶体管，第三MOS晶体管，第一分压电路，输出通过将输出端子的电压除以第一分压而得到的第一分压 以及馈送有参考电压的第一差分放大器电路和第一分压，并且具有连接到第二MOS晶体管的栅极的输出。 当第一分压高于参考电压时，第一差分放大器电路输出信号以接通第二MOS晶体管，并且当第一分压电压较低时，第一差分放大器电路输出关闭第二MOS晶体管的信号 比参考电压。

公开(公告)号：US20080101107A1

公开(公告)日：2008-05-01

申请号：US11877890

申请日：2007-10-24

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/00

CPC分类号： G11C11/22

摘要： A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell and a second plate line is connected to the second ferroelectric memory cell. A selection transistor has one end connected to the first and second ferroelectric memory cells and the other end connected to a bit-line.

摘要翻译： 第一铁电存储器单元和第二铁电存储单元各自包括铁电电容器和晶体管，并且每个存储一组信息。 字线由第一和第二铁电存储器单元共享。 第一板线连接到第一铁电存储单元，第二板线连接到第二铁电存储单元。 选择晶体管的一端连接到第一和第二铁电存储单元，另一端连接到位线。

公开(公告)号：US07269049B2

公开(公告)日：2007-09-11

申请号：US11046878

申请日：2005-02-01

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.

摘要翻译： 排列多个铁电存储单元。 排列在同一列中的每个存储单元的一个端子共同连接到第一位线。 排列在同一行中的存储单元的晶体管的栅极共同连接到字线。 排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。 第二位线与参考电压供应电路连接。 第一和第二位线与数据读取电路连接。 数据读取电路包括读出放大器和电流镜像电路，其具有连接到第一和第二位线的一对电流输入节点，并且将流过第一和第二位线之一的相同电流传送到另一位线。

公开(公告)号：US20060279977A1

公开(公告)日：2006-12-14

申请号：US11447940

申请日：2006-06-07

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of the ferroelectric capacitor. In a read operation of data, a first voltage is applied to the plate line. In a write operation of data, a second voltage different from the first voltage is applied to the plate line, and a voltage which is higher or lower than the second voltage is applied to the bit line.

摘要翻译： 铁电存储器件包括电池块，位线和板线。 电池块包括铁电电容器和晶体管开关。 位线向铁电电容器的一个电极施加电压。 板线向铁电电容器的另一个电极施加电压。 在数据的读取操作中，向板线施加第一电压。 在数据的写入操作中，不同于第一电压的第二电压被施加到板线，并且高于或低于第二电压的电压被施加到位线。

公开(公告)号：US08274846B2

公开(公告)日：2012-09-25

申请号：US12652612

申请日：2010-01-05

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C5/14

CPC分类号： G11C7/14 ,  G11C5/147 ,  G11C11/22

摘要： A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each capacitor comprising a first end connected to a connection node between the first and second switches and a second end settable at an independent voltage level, a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch, and then to turn on the first switch, and a voltage controller configured to individually set a voltage at the second end of each capacitor after the first switch is turned on.

摘要翻译： 参考电压产生电路包括可设置为参考电压的第一节点，其为多个电压电平中的任何一个，在预充电电压下设置的第二节点，串联连接在第一和第二节点之间的第一和第二开关， 多个电容器，每个电容器包括连接到第一和第二开关之间的连接节点的第一端和可设置在独立电压电平的第二端;开关控制器，被配置为关闭第一开关并将第二开关导通 初始状态，然后关闭第二开关，然后打开第一开关，并且电压控制器被配置为在第一开关导通之后单独设置每个电容器的第二端处的电压。

公开(公告)号：US20110044087A1

公开(公告)日：2011-02-24

申请号：US12684375

申请日：2010-01-08

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/06

CPC分类号： G11C11/22

摘要： A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.

摘要翻译： 存储器包括铁电电容器; 感测放大器，被配置为检测存储在铁电电容器中的数据; 以及板控制电路，被配置为接收驱动板线的板驱动信号，指示从外部向读出放大器写入数据的写入信号，以及指示可执行周期结束的操作结束信号，用于在 读出放大器和外部，板控制电路基于写入信号和操作结束信号来验证或使板驱动信号无效，其中板控制电路在可执行周期中验证板驱动信号，并且板控制电路使板 在可执行期间写入信号从不被激活的可执行期间结束时的驱动信号，并且在可执行期间写入信号被激活时，保持板驱动信号有效。

公开(公告)号：US07385836B2

公开(公告)日：2008-06-10

申请号：US11265188

申请日：2005-11-03

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a selection transistor which is connected at one end to the reference bit line, and a paraelectric capacitor connected between the other end of the selection transistor and a dummy plate line. A dummy plate line driver is connected to the dummy plate line. The dummy plate line driver drives the dummy plate line to a first voltage which is higher than an operating voltage of the sense amplifier circuit, when the reference potential generating circuit generates the reference potential.

摘要翻译： 向读出放大器电路提供参考电位的参考位线连接到读出放大器电路。 参考电位产生电路连接到参考位线。 参考电位产生电路包括一端连接到参考位线的选择晶体管和连接在选择晶体管的另一端和虚设板线之间的顺电电容器。 虚拟板线驱动器连接到虚拟板线。 当参考电位产生电路产生参考电位时，虚拟板线驱动器将虚拟板线驱动到高于读出放大器电路的工作电压的第一电压。

公开(公告)号：US20080068874A1

公开(公告)日：2008-03-20

申请号：US11898605

申请日：2007-09-13

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.

摘要翻译： 本公开涉及包括铁电电容器的半导体存储器件; 电池晶体管，其源极连接到所述铁电电容器的第一电极; 位线 字线 n列板对应于n列块，分别连接到相应列块中的铁电电容器的第二电极，n列块是通过将每个m列的单元阵列划分成n列块而获得的，其中 n> = 2且m> = 2; 多个复位晶体管，连接在所述位线与所述n条线之间; 和m个复位线，其对应于列块内的m列，并连接到复位晶体管的n个复位晶体管的栅极，n个复位晶体管分别设置在分别包含在n个列块中的n列中。