公开(公告)号：US20100263707A1

公开(公告)日：2010-10-21

申请号：US12762256

申请日：2010-04-16

申请人： Dan Daeweon Cheong ,  Rafael Nathan Kleiman ,  Manuela Peter ,  Nicholas Komarnycky ,  Bradley Joseph Robinson ,  John Stewart Preston

发明人： Dan Daeweon Cheong ,  Rafael Nathan Kleiman ,  Manuela Peter ,  Nicholas Komarnycky ,  Bradley Joseph Robinson ,  John Stewart Preston

IPC分类号： H01L31/05 ,  C30B23/02 ,  H01L21/20

CPC分类号： C30B25/183 ,  C30B23/02 ,  C30B23/025 ,  C30B29/40 ,  C30B29/42 ,  C30B29/44 ,  H01L31/1852 ,  Y02E10/544

摘要： The structure presented herein provides a base structure for semiconductor devices, in particular for III-V semiconductor devices or for a combination of III-V and Group IV semiconductor devices. The fabrication method for a base substrate comprises a buffer layer, a nucleation layer, a Group IV substrate and possibly a dopant layer. There are, in a general aspect, two growth steps: firstly the growth of a lattice-matched III-V material on a Group IV substrate, followed by secondly the growth of a lattice-mismatched III-V layer. The first layer, called the nucleation layer, is lattice-matched or closely lattice-matched to the Group IV substrate while the following layer, the buffer layer, deposited on top of the nucleation layer, is lattice-mismatched to the nucleation layer. The nucleation layer can further be used as a dopant source to the Group IV substrate, creating a p-n junction in the substrate through diffusion. Alternatively a separate dopant layer may be introduced.

摘要翻译： 本文中给出的结构提供了半导体器件的基础结构，特别是对于III-V半导体器件或III-V和IV族半导体器件的组合。 基底衬底的制造方法包括缓冲层，成核层，第IV族衬底和可能的掺杂剂层。 在一般方面，存在两个生长步骤：首先在IV族衬底上生长晶格匹配的III-V材料，其次是晶格失配的III-V层的生长。 称为成核层的第一层与第IV族基质晶格匹配或紧密地晶格匹配，而沉积在成核层顶部的下一层缓冲层与成核层晶格失配。 成核层可以进一步用作第IV族衬底的掺杂剂源，通过扩散在衬底中产生p-n结。 或者，可以引入单独的掺杂剂层。