公开(公告)号：US12084790B2

公开(公告)日：2024-09-10

申请号：US18337493

申请日：2023-06-20

Applicant: AXT, Inc.

Inventor： Rajaram Shetty ,  Weiguo Liu ,  Morris Young

IPC: C30B29/42 ,  C30B11/00 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/30 ,  H01S5/30

CPC classification number: C30B29/42 ,  C30B11/002 ,  C30B11/006 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/30 ,  H01S5/3013

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm−2, and a resistivity of 1×107 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm−1 less than 4 cm−1 or less than 3 cm−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm−3 or less.

公开(公告)号：US11680340B2

公开(公告)日：2023-06-20

申请号：US16711019

申请日：2019-12-11

Applicant: AXT, Inc.

Inventor： Rajaram Shetty ,  Weiguo Liu ,  Morris Young

IPC: C30B29/42 ,  C30B11/00 ,  H01L29/36 ,  H01L29/20 ,  H01L29/32 ,  H01L29/30 ,  H01S5/30

CPC classification number: C30B29/42 ,  C30B11/002 ,  C30B11/006 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/30 ,  H01S5/3013

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm−2, and a resistivity of 1×107 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm−1 less than 4 cm−1 or less than 3 cm−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm−3 or less.

公开(公告)号：US20190226119A1

公开(公告)日：2019-07-25

申请号：US16360576

申请日：2019-03-21

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Keisuke TANIZAKI ,  Yasuo NAMIKAWA

IPC: C30B29/42 ,  C30B11/00 ,  H01L27/15

CPC classification number: C30B29/42 ,  C30B11/00 ,  H01L27/15 ,  H01L33/16 ,  H01L33/30

Abstract: A GaAs crystal (35) has Δx(1) not greater than 20 cm−1 in an expression 1 Δ   x  ( 1 ) = ∑ i = 1 s   X i - X BL  s Expression   1 where xi represents a Raman shift of a first peak attributed to oscillation of a longitudinal optical phonon of GaAs in a Raman spectrum measured at an ith point in measurement of Raman spectra at s points in a (100) plane, xBL represents a Raman shift of an emission line peak of neon, and i and s are each a natural number greater than 0.

公开(公告)号：US09994936B2

公开(公告)日：2018-06-12

申请号：US13210138

申请日：2011-08-15

Applicant: Thomas Gmitter ,  Gang He ,  Melissa Archer ,  Siew Neo

Inventor： Thomas Gmitter ,  Gang He ,  Melissa Archer ,  Siew Neo

IPC: C30B19/00 ,  C22C29/00 ,  C30B33/06 ,  C30B29/42 ,  C30B29/40 ,  C30B33/08 ,  C30B29/00 ,  C30B33/10

CPC classification number: C22C29/00 ,  C30B29/00 ,  C30B29/40 ,  C30B29/42 ,  C30B33/06 ,  C30B33/08 ,  C30B33/10

Abstract: Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process- and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of at 0°.

公开(公告)号：US20180090316A1

公开(公告)日：2018-03-29

申请号：US15563599

申请日：2016-08-18

Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY

Inventor： Guoqiang LI ,  Fangliang GAO ,  Lei WEN ,  Shuguang ZHANG ,  Jingling LI

IPC: H01L21/02 ,  C30B29/42 ,  C30B25/18 ,  C30B25/10 ,  H01L21/324

CPC classification number: H01L21/02505 ,  C30B25/10 ,  C30B25/183 ,  C30B29/42 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02661 ,  H01L21/02694 ,  H01L21/3245 ,  H01L31/1852 ,  Y02E10/544

Abstract: Disclosed is a preparation method for a GaAs thin film grown on an Si substrate, said method comprising the following steps: (1) Si (111) substrate cleaning; (2) Si (111) substrate preprocessing; (3) Si (111) substrate oxide film removal; (4) first InxGa1-xAs buffer layer growth; (5) first InxGa1-xAs buffer layer in situ annealing; (6) GaAs buffer layer growth; (7) GaAs buffer layer in situ annealing; (8) second InxGa1-xAs buffer layer growth; (9) second InxGa1-xAs buffer layer in situ annealing; (10) GaAs epitaxial thin film growth. Also disclosed is a GaAs thin film grown on an Si substrate. The GaAs thin film obtained by the present invention has a good crystal quality, an even surface, and a positive promotional significance with regard to the preparation of semiconductor devices, particularly in the field of solar cells.

公开(公告)号：US20170183793A1

公开(公告)日：2017-06-29

申请号：US15455370

申请日：2017-03-10

Applicant: Government of the United States, as represented by the Secretary of the Air Force

Inventor： Vladimir L. Tassev ,  Rita D. Peterson

IPC: C30B25/04 ,  C30B29/42 ,  C30B29/44 ,  G02F1/355 ,  C30B25/18

CPC classification number: C30B25/04 ,  C30B25/18 ,  C30B29/42 ,  C30B29/44 ,  G02F1/3556 ,  G02F1/3558 ,  G02F1/39 ,  G02F2001/392 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/02543 ,  H01L21/02609 ,  H01L21/0262 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/036 ,  H01L31/109 ,  H01L31/1844

Abstract: A method of forming a layered OP material is provided, where the layered OP material comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more.

公开(公告)号：US20170051432A1

公开(公告)日：2017-02-23

申请号：US15255766

申请日：2016-09-02

Applicant: QUNANO AB

Inventor： Lars Samuelson ,  Martin Magnusson ,  Knut Deppert ,  Magnus Heurlin

IPC: C30B25/00 ,  C30B29/62 ,  C30B29/42 ,  C30B29/40

CPC classification number: C30B25/005 ,  B82Y30/00 ,  B82Y40/00 ,  C30B25/00 ,  C30B29/40 ,  C30B29/403 ,  C30B29/42 ,  C30B29/62

Abstract: The present invention provides a method and a system for forming wires (1) that enables a large scale process combined with a high structural complexity and material quality comparable to wires formed using substrate-based synthesis. The wires (1) are grown from catalytic seed particles (2) suspended in a gas within a reactor. Due to a modular approach wires (1) of different configuration can be formed in a continuous process. In-situ analysis to monitor and/or to sort particles and/or wires formed enables efficient process control.

Abstract translation: 本发明提供一种用于形成导线（1）的方法和系统，其使得能够与结构复杂性和材料质量相结合的大规模工艺与基于基板的合成形成的导线相比。 电线（1）从悬浮在反应器内的气体中的催化种子颗粒（2）生长。 由于模块化方法，可以在连续过程中形成不同配置的线（1）。 用于监测和/或排列形成的颗粒和/或线的原位分析可以有效地进行过程控制。

公开(公告)号：US09574286B2

公开(公告)日：2017-02-21

申请号：US14403427

申请日：2013-05-24

Applicant: SOL VOLTAICS AB

Inventor： Greg Alcott ,  Martin Magnusson ,  Olivier Postel ,  Knut Deppert ,  Lars Samuelson ,  Jonas Ohlsson

IPC: C30B25/00 ,  C30B25/02 ,  C30B29/06 ,  C30B29/40 ,  C30B11/00 ,  C30B11/12 ,  C30B29/62 ,  C30B29/60

CPC classification number: C30B25/14 ,  C23C16/301 ,  C23C16/45504 ,  C23C16/45519 ,  C30B11/003 ,  C30B11/006 ,  C30B11/12 ,  C30B23/007 ,  C30B25/005 ,  C30B25/025 ,  C30B29/06 ,  C30B29/40 ,  C30B29/403 ,  C30B29/42 ,  C30B29/60 ,  C30B29/62 ,  Y10T117/102

Abstract: A gas phase nanowire growth apparatus including a reaction chamber (200), a first input and a second input (202 B, 202 A). The first input is located concentrically within the second input and the first and second input are configured such that a second fluid delivered from the second input provides a sheath between a first fluid delivered from the first input and a wall of the reaction chamber. An aerosol of catalyst particles may be used to grow the nanowires.

Abstract translation: 一种气相纳米线生长装置，包括反应室（200），第一输入端和第二输入端（202B，202A）。 所述第一输入同心地位于所述第二输入内，并且所述第一和第二输入被配置为使得从所述第二输入端递送的第二流体在从所述第一输入端输送的第一流体与所述反应室的壁之间提供护套。 可以使用催化剂颗粒的气溶胶来生长纳米线。

公开(公告)号：US20160053404A1

公开(公告)日：2016-02-25

申请号：US14780280

申请日：2013-03-27

Applicant: BEIJING TONGMEI XTAL TECHNOLOGY CO., LTD.

Inventor： Morris YOUNG ,  Davis ZHANG ,  Vincent Wensen LIU ,  Yuanli WANG

IPC: C30B33/02 ,  C30B11/14 ,  C30B29/42 ,  H01L29/207 ,  C30B29/40 ,  H01L21/324 ,  H01L21/322 ,  H01L29/36 ,  C30B11/00 ,  C30B29/44

CPC classification number: C30B33/02 ,  C30B11/003 ,  C30B11/006 ,  C30B11/14 ,  C30B29/40 ,  C30B29/42 ,  C30B29/44 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/207 ,  H01L29/36

Abstract: A method of controlling oxygen concentration in III-V compound semiconductor substrate comprises providing a plurality of III-V crystal substrates in a container, providing a predetermined amount of material in the container. Atoms of the predetermined amount of material having a high chemical reactivity with oxygen atoms. The method further comprises maintaining a predetermined pressure within the container and annealing the plurality of III-V crystal substrates to yield an oxygen concentration in the crystal substrates. The oxygen concentration is associated with the predetermined amount of material.

Abstract translation: 控制III-V族化合物半导体衬底中的氧浓度的方法包括在容器中提供多个III-V晶体衬底，在容器中提供预定量的材料。 与氧原子具有高化学反应性的预定量的材料的原子。 该方法还包括保持容器内的预定压力并退火多个III-V晶体衬底以在晶体衬底中产生氧浓度。 氧浓度与预定量的材料相关联。

公开(公告)号：US20160043248A1

公开(公告)日：2016-02-11

申请号：US14780333

申请日：2014-03-11

Applicant: JX NIPPON MINING & METALS CORPORATION

Inventor： Akira NODA ,  Masaru OTA ,  Ryuichi HIRANO

IPC: H01L31/0304 ,  C30B29/40 ,  C30B15/30 ,  C30B15/04 ,  C30B15/20

CPC classification number: H01L31/03042 ,  C30B15/04 ,  C30B15/20 ,  C30B15/203 ,  C30B15/22 ,  C30B15/30 ,  C30B27/02 ,  C30B29/40 ,  C30B29/42 ,  H01L31/0735 ,  H01L31/184 ,  Y02E10/544 ,  Y02P70/521

Abstract: In this photoelectric conversion element wherein group III-IV compound semiconductor single crystals containing zinc as an impurity are used as a substrate, the substrate is increased in size without lowering conversion efficiency. A heat-resistant crucible is filled with raw material and a sealant, and the raw material and sealant are heated, thereby melting the raw material into a melt, softening the encapsulant, and covering the melt from the top with the encapsulant. The temperature inside the crucible is controlled such that the temperature of the top of the encapsulant relative to the bottom of the encapsulant becomes higher in a range that not equal or exceed the temperature of bottom of the encapsulant, and seed crystal is dipped in the melt and pulled upward with respect to the melt, thereby growing single crystals from the seed crystal. Thus, a large compound semiconductor wafer that is at least two inches in diameter and has a low dislocation density of 5,000 cm−2 can be obtained, despite having a low average zinc concentration of 5×1017 cm−3 to 3×1018 cm−3, at which a crystal hardening effect does not manifest.

Abstract translation: 在使用含有锌杂质的III-IV族化合物半导体单晶作为基板的光电转换元件中，基板的尺寸增大而不降低转换效率。 用原料和密封剂填充耐热坩埚，加热原料和密封剂，将原料熔融成熔融物，使密封剂软化，用密封剂从顶部覆盖熔融物。 控制坩埚内部的温度使得密封剂的顶部相对于密封剂的底部的温度在不等于或超过密封剂的底部温度的范围内变得更高，晶种浸入熔体中 并相对于熔体向上拉，从而从晶种生长单晶。 因此，尽管具有5×1017cm-3至3×1018cm -1的低平均锌浓度，但是可以获得直径至少为2英寸，位错密度为5000cm -2的大型化合物半导体晶片， 3，其中晶体硬化效果不显示。