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    Electronic digital governor and method of assembly
    1.
    发明授权
    Electronic digital governor and method of assembly 有权
    电子数字调速器及组装方法

    公开(公告)号：US08744731B2

    公开(公告)日：2014-06-03

    申请号：US13292472

    申请日：2011-11-09

    申请人： Dan Wertz ,  Kevin A. Batson ,  Dae Kon Yi ,  Sean Lavin ,  Paul Cappa

    发明人： Dan Wertz ,  Kevin A. Batson ,  Dae Kon Yi ,  Sean Lavin ,  Paul Cappa

    IPC分类号： G05B19/10 ,  G05B11/01

    CPC分类号： F02D31/001 ,  F02D29/06 ,  F02D41/28

    摘要： An electronic digital governor assembly includes a case, a printed circuit board housed within said case, the printed circuit board having control circuitry configured for controlling at least one parameter of an energy production device, and a user interface including a digital display for displaying a value of the at least one parameter and at least one button for selectively adjusting the value.

    摘要翻译： 电子数字调速器组件包括壳体，容纳在所述壳体内的印刷电路板，所述印刷电路板具有被配置为用于控制能量产生装置的至少一个参数的控制电路，以及包括用于显示值的数字显示器的用户界面 的至少一个参数和用于选择性地调整该值的至少一个按钮。

    ELECTRONIC DIGITAL GOVERNOR AND METHOD OF ASSEMBLY
    2.
    发明申请
    ELECTRONIC DIGITAL GOVERNOR AND METHOD OF ASSEMBLY 有权
    电子数字总监及其组装方法

    公开(公告)号：US20120123664A1

    公开(公告)日：2012-05-17

    申请号：US13292472

    申请日：2011-11-09

    申请人： Dan Wertz ,  Kevin A. Batson ,  Dae Kon Yi ,  Sean Lavin ,  Paul Cappa

    发明人： Dan Wertz ,  Kevin A. Batson ,  Dae Kon Yi ,  Sean Lavin ,  Paul Cappa

    IPC分类号： F02D45/00 ,  H01S4/00

    CPC分类号： F02D31/001 ,  F02D29/06 ,  F02D41/28

    摘要： An electronic digital governor assembly includes a case, a printed circuit board housed within said case, the printed circuit board having control circuitry configured for controlling at least one parameter of an energy production device, and a user interface including a digital display for displaying a value of the at least one parameter and at least one button for selectively adjusting the value.

    摘要翻译： 电子数字调速器组件包括壳体，容纳在所述壳体内的印刷电路板，所述印刷电路板具有被配置为用于控制能量产生装置的至少一个参数的控制电路，以及包括用于显示值的数字显示器的用户界面 的至少一个参数和用于选择性地调整该值的至少一个按钮。

    Programmable pulsewidth and delay generating circuit for integrated circuits
    4.
    发明授权
    Programmable pulsewidth and delay generating circuit for integrated circuits 有权
    用于集成电路的可编程脉冲宽度和延迟发生电路

    公开(公告)号：US07869302B2

    公开(公告)日：2011-01-11

    申请号：US12543256

    申请日：2009-08-18

    申请人： Rajiv V. Joshi ,  Robert Maurice Houle ,  Kevin A. Batson

    发明人： Rajiv V. Joshi ,  Robert Maurice Houle ,  Kevin A. Batson

    IPC分类号： G11C8/00

    CPC分类号： G11C11/413 ,  G11C11/41 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/1202 ,  G11C2029/1208 ,  H03K5/06 ,  H03K5/13 ,  H03K5/1565

    摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

    摘要翻译： 本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出​​本地时钟信号的时钟产生电路。 时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。 前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。 后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

    PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS
    5.
    发明申请
    PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS 失效
    集成电路的可编程脉宽调制和延迟发生电路

    公开(公告)号：US20080310246A1

    公开(公告)日：2008-12-18

    申请号：US11761655

    申请日：2007-06-12

    申请人： Rajiv V. Joshi ,  Robert Maurice Houle ,  Kevin A. Batson

    发明人： Rajiv V. Joshi ,  Robert Maurice Houle ,  Kevin A. Batson

    IPC分类号： G11C8/00 ,  H03K19/00 ,  H03K3/017

    CPC分类号： G11C11/413 ,  G11C11/41 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/1202 ,  G11C2029/1208 ,  H03K5/06 ,  H03K5/13 ,  H03K5/1565

    摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

    摘要翻译： 本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出​​本地时钟信号的时钟产生电路。 时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。 前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。 后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

    METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT
    6.
    发明申请
    METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT 有权
    用于在集成电路中校准内部脉冲的方法和装置

    公开(公告)号：US20080309364A1

    公开(公告)日：2008-12-18

    申请号：US11761610

    申请日：2007-06-12

    申请人： Rajiv V. Joshi ,  Robert L. Franch ,  Robert Maurice Houle ,  Kevin A. Batson

    发明人： Rajiv V. Joshi ,  Robert L. Franch ,  Robert Maurice Houle ,  Kevin A. Batson

    IPC分类号： G01R31/02

    CPC分类号： G01R31/31725 ,  G01R31/31726

    摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

    摘要翻译： 用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。 延迟链被配置为从片上电路部件接收脉冲信号。 采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。

    System and method for conserving power in a content addressable memory by providing an independent search line voltage
    9.
    发明授权
    System and method for conserving power in a content addressable memory by providing an independent search line voltage 有权
    通过提供独立的搜索线电压来节省内容可寻址存储器中的功率的系统和方法

    公开(公告)号：US06442055B1

    公开(公告)日：2002-08-27

    申请号：US10016025

    申请日：2001-12-12

    申请人： Robert E. Busch ,  Kevin A. Batson

    发明人： Robert E. Busch ,  Kevin A. Batson

    IPC分类号： G11C1500

    CPC分类号： G11C15/043 ,  G11C15/04

    摘要： A system and method is disclosed for operating a content addressable memory (CAM) within an integrated circuit using search signals at search input voltages which are substantially independent from an operating voltage of the CAM. A method is disclosed in which search signals are input to CAM cells of the CAM at search input voltages which are substantially independent of an operating voltage of storage elements within the CAM cells. A match signal is output upon detecting a matching condition between the search signals and data stored in the storage elements. The search input voltage can be within about 0.2V above a threshold voltage of a search input device of the CAM memory cell. Search input devices can be selected to have a lower threshold voltage than other devices included within the CAM cell.

    摘要翻译： 公开了一种用于在搜索输入电压下使用基本上独立于CAM的工作电压的搜索信号来操作集成电路内的内容可寻址存储器（CAM）的系统和方法。 公开了一种方法，其中搜索信号以基本上独立于CAM单元内的存储元件的工作电压的搜索输入电压输入到CAM的CAM单元。 在检测到搜索信号和存储在存储元件中的数据之间的匹配条件时输出匹配信号。 搜索输入电压可以在CAM存储器单元的搜索输入装置的阈值电压以上约0.2V内。 可以选择搜索输入设备以具有比包括在CAM单元内的其它设备更低的阈值电压。

    High reliability content-addressable memory using shadow content-addressable memory
    10.
    发明授权
    High reliability content-addressable memory using shadow content-addressable memory 有权
    高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存

    公开(公告)号：US06650561B2

    公开(公告)日：2003-11-18

    申请号：US10059863

    申请日：2002-01-30

    申请人： Kevin A. Batson ,  Geordie M. Braceras ,  Robert E. Busch ,  Gary S. Koch

    发明人： Kevin A. Batson ,  Geordie M. Braceras ,  Robert E. Busch ,  Gary S. Koch

    IPC分类号： G11C1500

    CPC分类号： G11C15/00

    摘要： A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

    摘要翻译： 使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。 阴影CAM与主CAM并行写入，读取和搜索。 比较并行搜索的搜索结果，如果相同，则声明为有效。 如果搜索结果不相等，则会启动纠正措施。 高可靠性内容寻址存储器可以与或不与优先编码器一起使用。