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1.发明申请STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS 有权辐射硬化三重模式冗余数字电路设计自动化的结构与方法公开(公告)号：US20120306535A1
公开(公告)日：2012-12-06
申请号：US13487859
申请日：2012-06-04
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. TheSSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。
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2.发明申请公开(公告)号：US20140331197A1
公开(公告)日：2014-11-06
申请号：US14304155
申请日：2014-06-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。
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3.发明申请RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR 审中-公开通过设计微处理器硬化辐射的辐射硬化结构扩展公开(公告)号：US20160065243A1
公开(公告)日：2016-03-03
申请号：US14837361
申请日：2015-08-27
CPC分类号： G06F9/30145 , G06F9/3861 , G06F9/3863 , G06F11/00
摘要： This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.
摘要翻译： 本公开一般涉及其操作处理器和方法。 特别地，本公开涉及用于校正处理器中的软错误的组件。 在一个实施例中，处理器包括指令解码器和异常处理程序。 指令解码器被配置为接收一个或多个软错误校正指令并对一个或多个软错误校正指令进行解码。 此外，异常处理程序被配置为执行一个或多个软错误校正指令，以便校正一个或多个软错误。 以这种方式，处理器能够校正作为辐射打击结果的软错误。
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4.发明授权公开(公告)号：US09038012B2
公开(公告)日：2015-05-19
申请号：US14304155
申请日：2014-06-13
IPC分类号： G06F17/50 , H03K19/173 , H03K19/003
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。
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公开(公告)号：US09734272B2
公开(公告)日：2017-08-15
申请号：US14739347
申请日：2015-06-15
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072
摘要： This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.
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6.发明申请TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE INTEGRATED CIRCUITS 有权用于生成硅多模式集成电路的物理层的技术公开(公告)号：US20150363517A1
公开(公告)日：2015-12-17
申请号：US14739347
申请日：2015-06-15
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072
摘要： This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.
摘要翻译： 本公开一般涉及具有计算机多模冗余（MMR）流水线电路的计算机集成电路（IC）的物理表示的计算机化系统和方法。 电子计算机IC的IC布局最初是通过电子设计自动化（EDA）程序生成的。 然后，在MMRSCSSE布局变得不稳定之后，多模式冗余自校正顺序状态元素（MMRSCSSE）布局变得不可移动，而从IC布局中删除初始冗余组合逻辑电路（CLC）布局。 首先放置MMRSCSSE布局，然后使它们变得不漂亮，剩下的逻辑可以重新放置并优化，而不会影响关键的节点间距。 因此，所描述的方法提供了一种更有效的方法来创建计算机IC的IC布局，同时保持关键的节点间隔。
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7.发明授权公开(公告)号：US08791718B2
公开(公告)日：2014-07-29
申请号：US13487859
申请日：2012-06-04
IPC分类号： H03K19/003
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states.The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs有一个自我纠正机制来防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。
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