-
公开(公告)号：US20070121714A1
公开(公告)日：2007-05-31
申请号：US11274687
申请日：2005-11-14
申请人： Daniel Baker , Barry McKibben , Michael Nakamura , Evan Albright , Scott Zink , Michael Overton
发明人： Daniel Baker , Barry McKibben , Michael Nakamura , Evan Albright , Scott Zink , Michael Overton
CPC分类号： H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
摘要： A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, such as a sine wave, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor is then used to subtract the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.
摘要翻译： 用于眼图的灵活时基使用稳定的自由运行振荡器作为采样时钟，用于等效时间采样输入串行数字信号和参考信号，例如从输入串行数字信号的细分恢复时钟导出的正弦波 。 将参考信号样本提供给数字锁相环，其向眼图发生器提供灵活的时基。 眼图发生器在对应于参考信号样本的时间累积输入的串行数字信号样本以产生眼图。 数字锁相环中的线性相位检测器使用希尔伯特变换将参考信号样本转换为复信号，然后使用具有反正切查找表的CORDIC算法将其转换为相位值的线性斜坡。 然后使用减法器从线性斜坡减去数字锁相环反馈，以向环路滤波器提供输入。
-
公开(公告)号：US5632029A
公开(公告)日：1997-05-20
申请号：US449398
申请日：1995-05-23
CPC分类号： G06F13/409 , G06F13/4022
摘要： A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.
摘要翻译： 采用多芯片封装和模块化共享总线实现的多级分层总线结构提供了高带宽。 所有IC组件均安装在标准化的多芯片封装上。 每个多芯片封装包括用于提供从集成电路到板总线的通信的总线接口芯片。 一个多芯片封装包含用于提供从板总线到背板总线的通信的附加总线接口电路。
-
公开(公告)号：US5978880A
公开(公告)日：1999-11-02
申请号：US447648
申请日：1995-05-23
CPC分类号： G06F13/409 , G06F13/4022
摘要： A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.
摘要翻译： 采用多芯片封装和模块化共享总线实现的多级分层总线结构提供了高带宽。 所有IC组件均安装在标准化的多芯片封装上。 每个多芯片封装包括用于提供从集成电路到板总线的通信的总线接口芯片。 一个多芯片封装包含用于提供从板总线到背板总线的通信的附加总线接口电路。
-
公开(公告)号：US5685004A
公开(公告)日：1997-11-04
申请号：US24877
申请日：1993-03-01
CPC分类号： G06F13/409 , G06F13/4022
摘要： A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.
-
-
-
搜索结果
4 条记录 (耗时 0.025 秒)
